SLVSEW1B April   2019  – April 2019 TPS566235

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
      2.      Efficiency vs Output Current Eco-mode
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation and D-CAP3 Control
      2. 7.3.2 Power Good
      3. 7.3.3 Soft Start and Pre-Biased Soft Start
      4. 7.3.4 Over current Protection and Undervoltage Protection
      5. 7.3.5 Over Voltage Protection
      6. 7.3.6 UVLO Protection
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Operation
      2. 7.4.2 MODE Pin Configuration
      3. 7.4.3 Advanced Eco-Mode Control
      4. 7.4.4 Out-Of-Audio Mode
      5. 7.4.5 Force CCM Mode
      6. 7.4.6 Standby Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Input Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

When laying out the printed circuit board, the following guideline should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 36

  • Recommend a four-layer PCB for good thermal performance and with maximum ground plane. 3" x 3", four-layer PCB with 2-oz. copper used as example.
  • Place the decoupling capacitors right across VIN as close as possible.
  • Place output inductors and capacitors with IC at the same layer, SW routing should be as short as possible to minimize EMI, and should be a wide plane to carry big current, enough vias should be added to the PGND connection of output capacitor and also as close to the output pin as possible.
  • Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane, >15 mil width trace is recommended to reduce line parasitic inductance.
  • FB could be wide and must be routed away from the switching node, BST node or other high efficiency signal.
  • VIN trace must be wide to reduce the trace impedance and provide enough current capability.
  • Place multiple vias near GND and near input capacitors to reduce parasitic inductance and improve thermal performance.