SLUSDQ7B May   2020  – December 2023 TPS566231 , TPS566238

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 PWM Operation and D-CAP3™ Control Mode
      2. 6.3.2 Soft Start
      3. 6.3.3 Power Good
      4. 6.3.4 Large Duty Operation
      5. 6.3.5 Overcurrent Protection and Undervoltage Protection
      6. 6.3.6 Overvoltage Protection
      7. 6.3.7 UVLO Protection
      8. 6.3.8 Output Voltage Discharge
      9. 6.3.9 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Advanced Eco-mode Control
      2. 6.4.2 Force CCM Mode
      3. 6.4.3 Standby Operation
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design with WEBENCH® Tools
        2. 7.2.2.2 Output Voltage Setpoint
        3. 7.2.2.3 Inductor Selection
        4. 7.2.2.4 Output Capacitor Selection
        5. 7.2.2.5 Input Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design with WEBENCH® Tools
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

PWM Operation and D-CAP3 Control Mode

The main control loop of the buck is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP3 control mode. D-CAP3 control mode combines adaptive on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The TPS56623x also includes an error amplifier that makes the output voltage very accurate.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after an internal one-shot timer expires. This one-shot duration is set proportional to the output voltage, VOUT, and is inversely proportional to the converter input voltage, VIN. This is done to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit is added to the reference voltage to emulate the output ripple. This enables the use of very low-ESR output capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation is required for D-CAP3 control mode.

For any control topology that is compensated internally, there is a range of the output filter it can support. The output filter used with the devices is a low-pass L-C circuit. This L-C filter has a double-pole frequency described in Equation 1.

Equation 1. GUID-F7196B38-F376-45ED-900F-80522FB3D4F2-low.gif

At low frequency, the overall loop gain is set by the output setpoint resistor divider network and the internal gain of the TPS56623x. The low-frequency L-C double pole has a 180 degree drop in-phase. At the output filter frequency, the gain rolls off at a –40-dB per decade rate and the phase drops rapidly. The internal ripple generation network introduces a high-frequency zero that reduces the gain rolloff from –40-dB to –20-dB per decade and leads the 90 degree phase boost. The internal ripple injection high-frequency zero is approximately 45 kHz. The inductor and capacitor selected for the output filter is recommended such that the double pole is located close to 1/3 the high-frequency zero. This is done so that the phase boost provided by this high-frequency zero provides adequate phase margin for the stability requirement. The crossover frequency of the overall system usually must be targeted to be less than one-third of the switching frequency (FSW).