SLVSD05G March   2016  – August 2024 TPS56C215

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  PWM Operation and D-CAP3™ Control Mode
      2. 6.3.2  Eco-mode Control
      3. 6.3.3  4.7-V LDO
      4. 6.3.4  MODE Selection
      5. 6.3.5  Soft Start and Prebiased Soft Start
      6. 6.3.6  Enable and Adjustable UVLO
      7. 6.3.7  Power Good
      8. 6.3.8  Overcurrent Protection and Undervoltage Protection
      9. 6.3.9  UVLO Protection
      10. 6.3.10 Thermal Shutdown
      11. 6.3.11 Output Voltage Discharge
    4. 6.4 Device Functional Modes
      1. 6.4.1 Light Load Operation
      2. 6.4.2 Standby Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 External Component Selection
          1. 7.2.2.1.1 Output Voltage Set Point
          2. 7.2.2.1.2 Switching Frequency and MODE Selection
          3. 7.2.2.1.3 Inductor Selection
          4. 7.2.2.1.4 Output Capacitor Selection
          5. 7.2.2.1.5 Input Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Marking

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.1 PWM Operation and D-CAP3™ Control Mode

The TPS56C215 operates using the adaptive on-time PWM control with a proprietary D-CAP3 control mode which enables low external component count with a fast load transient response while maintaining a good output voltage accuracy. At the beginning of each switching cycle, the high-side MOSFET is turned on for an on-time set by an internal one shot timer. This on-time is set based on the input voltage of the converter, output voltage of the converter, and the pseudo-fixed frequency, hence this type of control topology is called an adaptive on-time control. The one-shot timer resets and turns on again after the feedback voltage (VFB) falls below the internal reference voltage (VREF). An internal ramp is generated which is fed to the FB pin to simulate the output voltage ripple. This enables the use of very low-ESR output capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation is required for DCAP3 control topology.

The TPS56C215 includes an error amplifier that makes the output voltage very accurate. This error amplifier is absent in other flavors of DCAP3. For any control topology that is compensated internally, there is a range of the output filter it can support. The output filter used with the TPS56C215 is a low-pass L-C circuit. This L-C filter has double pole that is described in Equation 1.

Equation 1. TPS56C215

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS56C215. The low frequency L-C double pole has a 180 degree in-phase. At the output filter frequency, the gain rolls off at a –40-dB per decade rate and the phase drops rapidly. The internal ripple generation network introduces a high-frequency zero that reduces the gain roll off from –40-dB to –20-dB per decade and increases the phase to 90 degree one decade above the zero frequency. The internal ripple injection high frequency zero is changed according to the switching frequency selected as shown in Table 6-1. The inductor and capacitor selected for the output filter must be such that the double pole is located close enough to the high-frequency zero so that the phase boost provided by this high-frequency zero provides adequate phase margin for the stability requirement. The crossover frequency of the overall system must usually be targeted to be less than one-fifth of the switching frequency (FSW).

Table 6-1 Ripple Injection Zero
SWITCHING FREQUENCY (kHz)ZERO LOCATION (kHz)
4007.1
80014.3
120021.4

Table 6-2 lists the inductor values and part numbers that are used to plot the efficiency curves in Section 5.7.

Table 6-2 Inductor Values
VOUT(V)FSW(kHz)LOUT(μH)WÜRTH PART NUMBER(1)
1.24001.2744325120
8000.68744311068
12000.47744314047
3.34002.4744325240
8001.57443552150
12001.2744325120
5.54003.3744325330
8002.4744325240
12001.57443552150
(1) See Third-Party Products disclaimer.