SLVSGB5 August 2022 TPS56C231
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Pin | Type(1) | Description | |
---|---|---|---|
Name | No. | ||
BOOT | 1 | I | Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between BOOT and SW. |
VIN | 2,11 | P | Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and PGND. |
PGND | 3, 4, 5, 8, 9, 10 |
G | Power GND pin for the controller circuit and the internal circuitry. Connect to AGND with a short trace. |
SW | 6, 7 | O | Switch node pin. Connect the output inductor to this pin. |
AGND | 12 | G | Ground of internal analog circuitry. Connect AGND to the PGND plane with a short trace. |
FB | 13 | I | Converter feedback input. Connect to the center tap of the resistor divider between output voltage and AGND. |
SS | 14 | O | Soft-start time selection pin. Connecting an external capacitor sets the soft-start time and if no external capacitor is connected, the converter starts up in 1.2 ms. |
EN | 15 | I | Enable input control, leaving this pin floating enables the converter. This pin can also be used to adjust the input UVLO by connecting to the center tap of the resistor divider between VIN and EN. |
PGOOD | 16 | O | Open-drain power-good indicator. The pin is asserted low if output voltage is out of the PGOOD threshold, overvoltage, or if the device is under thermal shutdown, EN shutdown, or during soft start. |
VREG5 | 17 | I/O | 4.7-V internal LDO output that can also be driven externally with a 5-V input. This pin supplies voltage to the internal circuitry and gate driver. Bypass this pin with a 4.7-µF capacitor. |
MODE | 18 | I | Switching frequency, current limit selection, and light load operation mode selection pin. Connect this pin to a resistor divider from VREG5 and AGND for different MODE options shown in Table 7-2. |