SLVSDQ7B October 2016 – July 2021 TPS57114C-Q1
PRODUCTION DATA
The TPS57114C-Q1 device requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor with at least 4.7 µF of effective capacitance, and in some applications a bulk capacitance. The effective capacitance includes any dc-bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple-current rating greater than the maximum input-current ripple of the TPS57114C-Q1 device. Calculate the input ripple current using Equation 30.
The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the capacitor. One can minimize the capacitance variations due to temperature by selecting a dielectric material that is stable over temperature. The dielectrics usually selected for power regulator capacitors are X5R and X7R ceramic because they have a high capacitance-to-volume ratio and are fairly stable over temperature. Also select the output capacitor with the dc bias taken into account. The capacitance value of a capacitor decreases as the dc bias across that capacitor increases.
This example design requires a ceramic capacitor with at least a 10-V voltage rating to support the maximum input voltage. The selections for this example are one 10-µF and one 0.1-µF 10-V capacitor in parallel. The input capacitance value determines the input ripple voltage of the regulator. Calculate the input voltage ripple using Equation 31. Using the design example values, IO(max) = 4 A, C(IN) = 10 µF, and f(SW) = 1 MHz, yields an input-voltage ripple of 100 mV and an rms input-ripple current of 1.96 A.