SLVSD01B September   2015  – May 2019 TPS57140-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency vs Load Current
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope-Compensation Output Current
      3. 7.3.3  Bootstrap Voltage (Boot)
      4. 7.3.4  Low-Dropout Operation
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Voltage Reference
      7. 7.3.7  Adjusting the Output Voltage
      8. 7.3.8  Enable and Adjusting UVLO
      9. 7.3.9  Slow-Start or Tracking Pin (SS/TR)
      10. 7.3.10 Overload Recovery Circuit
      11. 7.3.11 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      12. 7.3.12 Overcurrent Protection and Frequency Shift
      13. 7.3.13 Selecting the Switching Frequency
      14. 7.3.14 How to Interface to RT/CLK Pin
      15. 7.3.15 Power Good (PWRGD Pin)
      16. 7.3.16 Overvoltage Transient Protection (OVTP)
      17. 7.3.17 Thermal Shutdown
      18. 7.3.18 Small-Signal Model for Loop Response
      19. 7.3.19 Simple Small-Signal Model for Peak-Current-Mode Control
      20. 7.3.20 Small-Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sequencing
      2. 7.4.2 Pulse-Skip Eco-mode Control Scheme
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the Switching Frequency
        2. 8.2.2.2  Output Inductor Selection (LO)
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Catch Diode
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Slow-Start Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  UVLO Set Point
        9. 8.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 8.2.2.10 Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power-Dissipation Estimate
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = –55°C to 150°C, VIN = 3.5 to 42 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 3.5 42 V
Internal UVLO threshold No voltage hysteresis, rising and falling 2.5 V
Shutdown supply current EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V 1.5 4 μA
EN = 0 V, 125°C, 3.5 V ≤ VIN ≤ 60 V 1.9 6.5
Operating: nonswitching supply current VSENSE = 0.83 V, VIN = 12 V, 25°C 116 140
ENABLE AND UVLO (EN PIN)
Enable threshold voltage No voltage hysteresis, rising and falling, 25°C 1.15 1.25 1.36 V
Input current Enable threshold 50 mV –3.8 μA
Enable threshold –50 mV –0.9
Hysteresis current –2.9 μA
VOLTAGE REFERENCE
Voltage reference TJ = 25°C 0.790 0.8 0.808 V
0.780 0.8 0.819
HIGH-SIDE MOSFET
On-resistance VIN = 3.5 V, BOOT-PH = 3 V 300 mΩ
VIN = 12 V, BOOT-PH = 6 V 200 410
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance (gm) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 97 μS
Error amplifier transconductance (gm) during slow start –2 μA < ICOMP < 2 μA, VCOMP = 1 V,
VVSENSE = 0.4 V		 26 μS
Error amplifier dc gain VVSENSE = 0.8 V 10 000 V/V
Error amplifier bandwidth 2700 kHz
Error amplifier source/sink V(COMP) = 1 V, 100-mV overdrive ±7 μA
COMP to switch current transconductance 6 S
CURRENT LIMIT
Current-limit threshold VIN = 12 V, TJ = 25°C 1.8 2.7 A
THERMAL SHUTDOWN
Thermal shutdown 182 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching-frequency range using RT mode VIN = 12 V 100 2500 kHz
fSW Switching frequency VIN = 12 V, RT = 200 kΩ 450 581 720 kHz
Switching-frequency range using CLK mode VIN = 12 V 300 2200 kHz
Minimum CLK pulse duration 40 ns
RT/CLK high threshold VIN = 12 V 1.9 2.2 V
RT/CLK low threshold VIN = 12 V 0.45 0.7 V
RT/CLK falling-edge to PH rising-edge delay Measured at 500 kHz with RT resistor in series 60 ns
PLL lock in time Measured at 500 kHz 100 μs
SLOW START AND TRACKING (SS/TR)
Charge current VSS/TR = 0.4 V 2 μA
SS/TR-to-VSENSE matching VSS/TR = 0.4 V 45 mV
SS/TR-to-reference crossover 98% nominal 1 V
SS/TR discharge current (overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 112 μA
SS/TR discharge voltage VSENSE = 0 V 54 mV
POWER GOOD (PWRGD PIN)
VVSENSE VSENSE threshold VSENSE falling 92%
VSENSE rising 94%
VSENSE rising 109%
VSENSE falling 107%
Hysteresis VSENSE falling 2%
Output-high leakage VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C 10 nA
On-resistance I(PWRGD) = 3 mA, VSENSE < 0.79 V 50 Ω
Minimum VIN for defined output V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA 0.95 1.5 V
TPS57140-EP D019_SLVSD01.gif
1. Electromigration fail mode = Time at temperature with bias
2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).
3. The predicted operating lifetime versus junction temperature is based on reliability modeling and available qualification data.
Figure 1. Predicted Lifetime Derating Chart for TPS57140-EP