SLVSD01B September   2015  – May 2019 TPS57140-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency vs Load Current
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope-Compensation Output Current
      3. 7.3.3  Bootstrap Voltage (Boot)
      4. 7.3.4  Low-Dropout Operation
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Voltage Reference
      7. 7.3.7  Adjusting the Output Voltage
      8. 7.3.8  Enable and Adjusting UVLO
      9. 7.3.9  Slow-Start or Tracking Pin (SS/TR)
      10. 7.3.10 Overload Recovery Circuit
      11. 7.3.11 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      12. 7.3.12 Overcurrent Protection and Frequency Shift
      13. 7.3.13 Selecting the Switching Frequency
      14. 7.3.14 How to Interface to RT/CLK Pin
      15. 7.3.15 Power Good (PWRGD Pin)
      16. 7.3.16 Overvoltage Transient Protection (OVTP)
      17. 7.3.17 Thermal Shutdown
      18. 7.3.18 Small-Signal Model for Loop Response
      19. 7.3.19 Simple Small-Signal Model for Peak-Current-Mode Control
      20. 7.3.20 Small-Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sequencing
      2. 7.4.2 Pulse-Skip Eco-mode Control Scheme
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the Switching Frequency
        2. 8.2.2.2  Output Inductor Selection (LO)
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Catch Diode
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Slow-Start Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  UVLO Set Point
        9. 8.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 8.2.2.10 Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power-Dissipation Estimate
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.3 Output Capacitor

The three primary considerations for selecting the value of the output capacitor are: the output capacitor determines the modulator pole, the output-voltage ripple, and how the regulator responds to a large change in load current. Select the output capacitance based on the most stringent of these three criteria.

The desired response to a large change in the load current is the first criterion. The output capacitor must supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator also temporarily is not able to supply sufficient output current if there is a large, fast increase in the current needs of the load, such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output-capacitor size must be adequate to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for two clock cycles while only allowing a tolerable amount of droop in the output voltage. Calculate the minimum output capacitance necessary to accomplish this using Equation 32.

For this example, the transient load response is specified as a 4% change in Vout for a load step from 0 A (no load) to 1.5 A (full load). For this example, ΔIout = 1.5 – 0 = 1.5 A and ΔVout = 0.04 × 3.3 V = 0.132 V. Using these numbers gives a minimum capacitance of 18.9 μF. This value does not take the ESR of the output capacitor into account in the output-voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that the designer must take into account.

The catch diode of the regulator cannot sink current, so any stored energy in the inductor produces an output voltage overshoot when the load current rapidly decreases, see Figure 53. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. The excess energy that is stored in the output capacitor increases the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. UseEquation 33 to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. For this example, the worst-case load step is from 1.5 to 0 A. The output voltage increases during this load transition, and the stated maximum in our specification is 4% of the output voltage. This makes Vf = 1.04 × 3.3 = 3.432. Vi is the initial capacitor voltage, which is the nominal output voltage of 3.3 V. Using these numbers in Equation 33 yields a minimum capacitance of 25.3 μF.

Use Equation 34 to calculate the minimum output capacitance needed to meet the ripple specification for output voltage. Equation 34 yields 0.7 μF.

Use Equation 35 to calculate the maximum ESR an output capacitor can have to meet the ripple specification for the output voltage. Equation 35 indicates the ESR should be less than 147 mΩ.

The most stringent criterion for the output capacitor is 25.3 μF of capacitance to keep the output voltage in regulation during an unload transient.

Factor in additional capacitance deratings for aging, temperature, and dc bias, increasing this minimum value. For this example, select a 47-μF 6.3-V X7R ceramic capacitor with 5 mΩ of ESR.

Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. Specify an output capacitor that can support the inductor ripple current. Some capacitor data sheets specify the root-mean-square (RMS) value of the maximum ripple current. Use Equation 36 to calculate the RMS ripple current that the output capacitor must support. For this application, Equation 36 yields 64.8 mA.

Equation 32. TPS57140-EP q_cout1_lvs795.gif

where

  • ΔIout is the change in output current.
  • ƒSW is the switching frequency of the regulator.
  • ΔVout is the allowable change in the output voltage.
Equation 33. TPS57140-EP q_cout2_lvs795.gif

where

  • L is the value of the inductor.
  • IOH is the output current under heavy load.
  • IOL is the output under light load.
  • VF is the final peak output voltage.
  • Vi is the initial capacitor voltage
Equation 34. TPS57140-EP q_cout3_lvs795.gif

where

  • ƒSW is the switching frequency.
  • Voripple is the maximum allowable output-voltage ripple.
  • Iripple is the ripple current of the inductor.
Equation 35. TPS57140-EP q_resr_lvs795.gif
Equation 36. TPS57140-EP q_icoutrms_lvs795.gif