SLVSAP3D December   2010  – February 2016 TPS57140-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope-Compensation Output Current
      3. 7.3.3  Low-Dropout Operation and Bootstrap Voltage (Boot)
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout (UVLO)
      8. 7.3.8  Slow-Start and Tracking Pin (SS/TR)
      9. 7.3.9  Overload Recovery Circuit
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 7.3.11 Overcurrent Protection and Frequency Shift
      12. 7.3.12 Selecting the Switching Frequency
      13. 7.3.13 How to Interface to RT/CLK Pin
      14. 7.3.14 Power Good (PWRGD Pin)
      15. 7.3.15 Overvoltage Transient Protection
      16. 7.3.16 Thermal Shutdown
      17. 7.3.17 Small-Signal Model for Loop Response
      18. 7.3.18 Simple Small-Signal Model for Peak-Current-Mode Control
      19. 7.3.19 Small-Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sequencing
      2. 7.4.2 Pulse-Skip Eco-mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the Switching Frequency
        2. 8.2.2.2  Output Inductor Selection (LO)
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Catch Diode
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Slow-Start Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Undervoltage Lockout (UVLO) Set Point
        9. 8.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 8.2.2.10 Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Estimate
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

Layout is a critical portion of good power supply design. Several signals paths conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. Figure 65 shows the PCB layout example. Obtaining acceptable performance with alternate PCB layouts may be possible, however this layout has been shown to produce good results and is meant as a guideline.

The following layout guidelines should be followed to achieve good system performance:

  • Providing a low-inductance, low-impedance ground path is critical. Therefore, use wide and short traces for the main current paths.
  • Care should be taken to minimize the loop area formed by the input bypass capacitor, VIN pin, PH pin, catch diode, inductor, and output capacitors. Use thick planes and traces to connect these components. For operation at a full-rated load, the top-side ground area must provide adequate heat dissipating area.
  • The GND pin should be tied directly to the thermal pad under the device and the thermal pad.
  • The thermal pad should be connected to any internal PCB ground planes using multiple vias directly under the device.
  • The PH pin should be routed to the cathode of the catch diode and to the output inductor. Because the PH connection is the switching node, the catch diode and output inductor should be located close to the PH pins,
  • Place the VSENSE voltage-divider resistor network away from switching node and route the feedback trace with minimum interaction with any noise sources associated with the switching components.
  • The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the device and should be routed with minimal lengths of trace.
  • Place compensation network components away from switching components and route the connections away from noisy area.
  • The bootstrap capacitor must be placed as close as possible to the IC pin.

10.2 Layout Example

TPS57140-Q1 layout_lvs795.gif Figure 65. PCB Layout Example

10.3 Power Dissipation Estimate

The following formulas show how to estimate power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM).

The power dissipation of the device includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd), and supply current loss (Pq).

Equation 54. TPS57140-Q1 eq56_lvs922.gif

where

  • IO is the output current (A).
  • RDS(on) is the on-resistance of the high-side MOSFET (Ω).
  • VOUT is the output voltage (V).
  • VIN is the input voltage (V).
Equation 55. TPS57140-Q1 eq57_lvs922.gif

where

  • ƒsw is the switching frequency (Hz).
Equation 56. TPS57140-Q1 eq58_lvs922.gif
Equation 57. TPS57140-Q1 eq59_lvs922.gif

Therefore:

Equation 58. TPS57140-Q1 eq60_lvs922.gif

where

  • Ptot is the total device power dissipation (W).

For given TA,

Equation 59. TPS57140-Q1 eq61_lvs922.gif

where

  • TA is the ambient temperature (°C).
  • TJ is the junction temperature (°C).
  • θJA is the thermal resistance of the package (°C/W).

For given TJ(MAX) = 150°C

Equation 60. TPS57140-Q1 eq62_lvs922.gif

where

  • TJ(MAX) is maximum junction temperature (°C).
  • TA(MAX) is maximum ambient temperature (°C).

Additional power losses occur in the regulator circuit because of the inductor ac and dc losses, the catch diode, and trace resistance that impact the overall efficiency of the regulator.