SGLS246B June 2004 – October 2016 TPS60400-Q1 , TPS60401-Q1 , TPS60402-Q1 , TPS60403-Q1
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
Package Options
Refer to the PDF data sheet for device specific package drawings
Mechanical Data (Package|Pins)
- DBV|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS6040x-Q1 family of devices generate an unregulated negative output voltage from an input voltage ranging from 1.8 V to 5.25 V.
9.2 Typical Applications
The most common application for these devices is a charge-pump voltage inverter (see Figure 23). This application requires only two external components; capacitors C(fly) and CO, plus a bypass capacitor, if necessary. See Capacitor Selection for suggested capacitor types.
Figure 23. Typical Operating Circuit
9.2.1 Design Requirements
The TPS6040x-Q1 is connected to generate a negative output voltage with 60-mA maximum load, from a positive input voltage between 1.8 V and 5.25 V.
9.2.2 Detailed Design Procedure
For the maximum output current and best performance, three ceramic capacitors of 1 μF (TPS60400-Q1, TPS60403-Q1) are recommended. For lower currents or higher allowed output voltage ripple, other capacitors can also be used. TI recommends the output capacitors has a minimum value of 1 μF. With flying capacitors lower than 1 μF, the maximum output power will decrease.
9.2.2.1 Capacitor Selection
To maintain the lowest output resistance, use capacitors with low ESR (see Table 2). The charge-pump output resistance is a function of the ESR of C(fly) and CO. Therefore, minimizing the ESR of the charge-pump capacitor minimizes the total output resistance. The capacitor values are closely linked to the required output current and the output noise and ripple requirements. It is possible to only use 1-μF capacitors of the same type. Ceramic capacitors will provide the lowest output voltage ripple because they typically have the lowest ESR-rating.
Table 2. Recommended Capacitor Values
| DEVICE | VI [V] | IO [mA] | CI [µF] | C(fly) [µF] | CO [µF] |
|---|---|---|---|---|---|
| TPS60400 | 1.8 to 5.25 | 60 | 1 | 1 | 1 |
| TPS60401 | 1.8 to 5.25 | 60 | 10 | 10 | 10 |
| TPS60402 | 1.8 to 5.25 | 60 | 3.3 | 3.3 | 3.3 |
| TPS60403 | 1.8 to 5.25 | 60 | 1 | 1 | 1 |
9.2.2.2 Input Capacitor (CI)
Bypass the incoming supply to reduce AC impedance and the impact of the TPS6040x-Q1 switching noise. The recommended bypassing depends on the circuit configuration and where the load is connected. When the inverter is loaded from OUT to GND, current from the supply switches between 2 × IO and zero. Therefore, use a large bypass capacitor (for example, equal to the value of C(fly)) if the supply has high AC impedance. When the inverter is loaded from IN to OUT, the circuit draws 2 × IO constantly, except for short switching spikes. A 0.1-μF bypass capacitor is sufficient.
9.2.2.3 Flying Capacitor (C(fly))
Increasing the flying capacitor’s size reduces the output resistance. Small values increases the output resistance. Above a certain point, increasing the capacitance of C(fly) has a negligible effect, because the output resistance becomes dominated by the internal switch resistance and capacitor ESR.
9.2.2.4 Output Capacitor (CO)
Increasing the output capacitor’s size reduces the output ripple voltage. Decreasing its ESR reduces both output resistance and ripple. Smaller capacitance values can be used with light loads if higher output ripple can be tolerated. Use Equation 6 to calculate the peak-to-peak ripple.
9.2.2.5 Power Dissipation
As given in Thermal Information, the thermal resistance of the unsoldered package is RθJA = 221.2°C/W. Soldered on the EVM, a typical thermal resistance of RθJA(EVM) = 180°C/W was measured. The terminal resistance can be calculated using Equation 7.
where
- TJ is the junction temperature
- TA is the ambient temperature
- PD is the power that needs to be dissipated by the device
The maximum power dissipation can be calculated using Equation 8.
The maximum power dissipation happens with maximum input voltage and maximum output current.
At maximum load the supply current is 0.7 mA maximum (see Equation 9).
With this maximum rating and the thermal resistance of the device on the EVM, the maximum temperature rise above ambient temperature can be calculated using Equation 10.
This means that the internal dissipation increases TJ by < 10°C.
The junction temperature of the device shall not exceed 125°C.
This means the device can easily be used at ambient temperatures up to Equation 11.
9.3 System Examples
9.3.1 RC-Post Filter
To reduce the output voltage ripple a RC-post filter can be used (Figure 26).
Figure 26. TPS60400 and TPS60401 With RC-Post Filter
An output filter can easily be formed with a resistor (RP) and a capacitor (CP). Cutoff frequency is given by Equation 12.
The ratio VO/VOUT is determined by Equation 13.
The formula refers only to the relation between output and input of the ac ripple voltages of the filter.
9.3.2 LC-Post Filter
To reduce the output voltage ripple, an LC-post filter can be used.
Figure 27 shows a configuration with a LC-post filter to further reduce output ripple and noise.
Figure 27. LC-Post Filter
Table 3 contains the typical measurement results using the TPS60400-Q1 device.
Table 3. Measurement Results on the TPS60400-Q1 (Typical)
| VI
[V] |
IO(2)
[mA] |
CI
[µF] CERAMIC |
C(fly)
[µF] CERAMIC |
CO
[µF] CERAMIC |
LP
[µH] |
CP
[µF] CERAMIC |
BW = 500 MHz VPOUT VP–P [mV] |
BW = 20 MHz VPOUT VP–P [mV] |
VPOUT
VACeff [mV] |
|---|---|---|---|---|---|---|---|---|---|
| 5 | 60 | 1 | 1 | 1 | 320 | 240 | 65 | ||
| 5 | 60 | 1 | 1 | 2.2 | 120 | 240 | 32 | ||
| 5 | 60 | 1 | 1 | 1 | 0.1 (X7R) | 260 | 200 | 58 | |
| 5 | 60 | 1 | 1 | 1 | 0.1 | 0.1 (X7R) | 220 | 200 | 60 |
| 5 | 60 | 1 | 1 | 2.2 | 0.1 | 0.1 (X7R) | 120 | 100 | 30 |
| 5 | 60 | 1 | 1 | 10 | 0.1 | 0.1 (X7R) | 50 | 28 | 8 |
9.3.3 Rail Splitter
A switched-capacitor voltage inverter can be configured as a high efficiency rail-splitter. This circuit provides a bipolar power supply that is useful in battery powered systems to supply dual-rail ICs, like operational amplifiers. Moreover, the SOT23-5 package and associated components require very little board space.
The maximum input voltage between VI and GND in Figure 28 (or between IN and OUT at the device itself) must not exceed 6.5 V.
Figure 28. TPS60400 as a High-Efficiency Rail Splitter
After power is applied, the flying capacitor (C(fly)) connects alternately across the output capacitors C3 and CO. This equalizes the voltage on those capacitors and draws current from VI to VO as required to maintain the output at 1/2 VI.
9.3.4 Combined Doubler/Inverter
The application allows to generate a voltage rail at a level of -Vi as well as 2 x Vi (V(pos)).
In the circuit of Figure 29, capacitors CI, C(fly), and CO form the inverter, while C1 and C2 form the doubler. C1 and C(fly) are the flying capacitors; CO and C2 are the output capacitors. Because both the inverter and doubler use part of the charge-pump circuit, loading either output causes both outputs to decline toward GND. Make sure the sum of the currents drawn from the two outputs does not exceed 60 mA. The maximum output current at V(pos) must not exceed 30 mA. If the negative output is loaded, this current must be further reduced.
Figure 29. TPS60400-Q1 as Doubler/Inverter
9.3.5 Cascading Devices
Two devices can be cascaded to produce an even larger negative voltage (see Figure 30). The unloaded output voltage is normally −2 × VI, but this is reduced slightly by the output resistance of the first device multiplied by the quiescent current of the second. When cascading more than two devices, the output resistance rises dramatically.
Figure 30. Doubling Inverter
9.3.6 Paralleling Devices
Paralleling multiple TPS6040x-Q1s reduces the output resistance. Each device requires its own flying capacitor (C(fly)), but the output capacitor (CO) serves all devices (see Figure 31). Increase CO’s value by a factor of n, where n is the number of parallel devices. Equation 2 shows the equation for calculating output resistance.
Figure 31. Paralleling Devices
9.3.7 Shutting Down the TPS6040x-Q1
If shutdown is necessary, use the circuit in Figure 32. The output resistance of the TPS6040x-Q1 will typically be 15 Ω plus two times the output resistance of the buffer.
Connecting multiple buffers in parallel can reduce the output resistance of the buffer driving the IN pin.
Figure 32. Shutdown Control
9.3.8 GaAs Supply
A solution for a –2.7-V/3-mA GaAs bias supply is proposed in Figure 33. The input voltage of 3.3 V is first inverted with a TPS60403-Q1 and stabilized using a TLV431 low-voltage shunt regulator. Resistor RP with capacitor CP is used for filtering the output voltage.
Figure 33. GaAs Supply
A 0.1-μF capacitor was selected for C(fly). By this, the output resistance of the inverter is about 52 Ω.
RPMAX can be calculated using Equation 14.
A 100-Ω resistor was selected for RP.
The reference voltage across R2 is 1.24 V typical. With 5-μA current for the voltage divider, R2 gets Equation 16 to Equation 17.
With: VCO = −3.3 V; VO = −2.7 V; IO = −3 mA
RPMAX = 200 Ω − 52 Ω = 148 Ω
With CP = 1 μF the ratio VO/VI of the RC post filter is Equation 18.
9.3.9 Step-Down Charge Pump
The application generates an output voltage of 1/2 of the input voltage.
By exchanging GND with OUT (connecting the GND pin with OUT and the OUT pin with GND), a step-down charge pump can easily be formed. In the first cycle S1 and S3 are closed, and C(fly) with CO in series are charged. Assuming the same capacitance, the voltage across C(fly) and CO is split equally between the capacitors. In the second cycle, S2 and S4 close and both capacitors with VI/2 across are connected in parallel.
Figure 34. Step-Down Principle
Figure 35. Step-Down Charge Pump Connection
The maximum input voltage between VI and GND in the schematic (or between IN and OUT at the device itself) must not exceed 5.5 V. For input voltages in the range of 5.5 V to 11 V, an additional Zener-diode is recommended (see Figure 36).
Figure 36. Step-Down Charge Pump Connection With Additional Zener Diode