Table 2. Design Parameters

9.2.1.2.1 Output Program

To program the output voltage, select the values of R1 and R2 (see Figure 7) according to Equation 1.

Equation 1.

A recommended value for R2 is approximately 10-kΩ which sets the current in the resistor divider chain to 0.5V/10kΩ = 50-μA. The output voltage tolerance depends on the VFB accuracy and the resistor divider.

Figure 7. Resistor Divider to Program Output Voltage

9.2.1.2.2 Without Isolation FET

The efficiency of the TPS61093-Q1 can be improved by connecting the load to the VO pin instead of the OUT pin. The power loss in the isolation FET is then negligible, as shown in Figure 8. The tradeoffs when bypassing the isolation FET are:

• Leakage path between input and output causes the output to be a diode drop below the input voltage when the IC is in shutdown
• No overload circuit protection

When the load is connected to the VO pin, the output capacitor on the VO pin should be above 1-μF.

Figure 8. Efficiency vs. Load

9.2.1.2.3 Start Up

The TPS61093-Q1 turns on the isolation FET and PWM switch when the EN pin is pulled high. During the soft start period, the R and C network on the SS pin is charged by an internal bias current of 5-μA (typ). The RC network sets the reference voltage ramp up slope. Since the output voltage follows the reference voltage via the FB pin, the output voltage rise time follows the SS pin voltage until the SS pin voltage reaches 0.5-V. The soft start time is given by Equation 2.

Equation 2.

where

• C5 is the capacitor connected to the SS pin

When the EN pin is pulled low to switch the IC off, the SS pin voltage is discharged to zero by the resistor R3. The discharge period depends on the RC time constant. Note that if the SS pin voltage is not discharged to zero before the IC is enabled again, the soft start circuit may not slow the output voltage startup and may not reduce the startup inrush current.

9.2.1.2.4 Switch Duty Cycle

The maximum switch duty cycle (D) of the TPS61093-Q1 is 90% (minimum). The duty cycle of a boost converter under continuous conduction mode (CCM) is given by:

Equation 3.

The duty cycle must be lower than the specification in the application; otherwise the output voltage cannot be regulated.

The TPS61093-Q1 has a minimum ON pulse width once the PWM switch is turned on. As the output current drops, the device enters discontinuous conduction mode (DCM). If the output current drops extremely low, causing the ON time to be reduced to the minimum ON time, the TPS61093-Q1 enters pulse-skipping mode. In this mode, the device keeps the power switch off for several switching cycles to keep the output voltage in regulation. See Figure 14. The output current when the IC enters skipping mode is calculated with Equation 4.

Equation 4.

where

• T_{min_on} = Minimum ON pulse width specification (typically 65-ns);
• L = Selected inductor value;
• f_SW = Converter switching frequency (typically 1.2-MHz)

9.2.1.2.5 Inductor Selection

Because the selection of the inductor affects steady state operation, transient behavior, and loop stability, the inductor is the most important component in power regulator design. There are three important inductor specifications, inductor value, saturation current, and dc resistance. Considering inductor value alone is not enough.

The saturation current of the inductor should be higher than the peak switch current as calculated in Equation 5.

Equation 5.

where

• I_{L_peak} = Peak switch current
• I_{L_DC} = Inductor average current
• ΔI_L = Inductor peak to peak current
• η = Estimated converter efficiency

Normally, it is advisable to work with an inductor peak-to-peak current of less than 30% of the average inductor current. A smaller ripple from a larger valued inductor reduces the magnetic hysteresis losses in the inductor and EMI. But in the same way, load transient response time is increased. Also, the inductor value should not be outside the 2.2-μH to 10-μH range in the recommended operating conditions table. Otherwise, the internal slope compensation and loop compensation components are unable to maintain small signal control loop stability over the entire load range. Table 3 lists the recommended inductor for the TPS61093-Q1.

9.2.1.2.6 Input And Output Capacitor Selection

The output capacitor is mainly selected to meet the requirements for output ripple and loop stability. This ripple voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a ceramic capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by:

Equation 6.

where

• V_ripple = peak to peak output ripple

The ESR impact on the output ripple must be considered if tantalum or electrolytic capacitors are used.

Care must be taken when evaluating a ceramic capacitor’s derating under dc bias, aging, and ac signal. For example, larger form factor capacitors (in 1206 size) have their self resonant frequencies in the range of the switching frequency. So the effective capacitance is significantly lower. The dc bias can also significantly reduce capacitance. A ceramic capacitor can lose as much as 50% of its capacitance at its rated voltage. Therefore, always leave margin on the voltage rating to ensure adequate capacitance at the required output voltage.

A 4.7-μF (minimum) input capacitor is recommended. The output requires a capacitor in the range of 1 μF to 10 μF. The output capacitor affects the small signal control loop stability of the boost regulator. If the output capacitor is below the range, the boost regulator can potentially become unstable.

The popular vendors for high value ceramic capacitors are:

• TDK (http://www.component.tdk.com/components.php)
• Murata (http://www.murata.com/cap/index.html)

9.2.1.2.7 Small Signal Stability

The TPS61093-Q1 integrates slope compensation and the RC compensation network for the internal error amplifier. Most applications will be control loop stable if the recommended inductor and input/output capacitors are used. For those few applications that require components outside the recommended values, the internal error amplifier’s gain and phase are presented in Figure 9.

Figure 9. Bode Plot of Error Amplifier Gain and Phase

The RC compensation network generates a pole f_p-ea of 57-kHz and a zero f_z-ea of 1.9-kHz, shown in Figure 9. Use Equation 7 to calculate the output pole, f_P, of the boost converter. If f_P << f_z-ea. due to a large capacitor beyond 10 μF, for example, a feed forward capacitor on the resistor divider, as shown in Figure 9, is necessary to generate an additional zero f_z-f. to improve the loop phase margin and improve the load transient response. The low frequency pole f_p-f and zero f_z-f generated by the feed forward capacitor are given by Equation 8 and Equation 9:

Equation 7.

Equation 8.

Equation 9.

where

• C_ff = the feed-forward capacitor

For example, in the typical application circuitry (see Figure 7), the output pole f_P is approximately 1-kHz. When the output capacitor is increased to 100-μF, then the f_P is reduced to 10-Hz. Therefore, a feed-forward capacitor of 10-nF compensates for the low frequency pole.

A feed forward capacitor that sets f_z-f near 10-kHz improves the load transient response in most applications, as shown in Figure 11.

Table 4. Design Parameters