SLVS427D JUNE   2002  – May 2015 TPS61120 , TPS61121 , TPS61122

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Controller Circuit
      2. 9.3.2 Synchronous Rectifier
      3. 9.3.3 LDO
      4. 9.3.4 Device Enable
        1. 9.3.4.1 Undervoltage Lockout
        2. 9.3.4.2 Softstart
      5. 9.3.5 LDO Enable
      6. 9.3.6 Power Good
      7. 9.3.7 Low Battery Detector Circuit—LBI/LBO
      8. 9.3.8 Low-EMI Switch
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Save Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Solution for Maximum Output Power
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Programming the Output Voltage
            1. 10.2.1.2.1.1 DC-DC Converter
            2. 10.2.1.2.1.2 LDO
          2. 10.2.1.2.2 Programming the LBI/LBO Threshold Voltage
          3. 10.2.1.2.3 Inductor Selection
          4. 10.2.1.2.4 Capacitor Selection
            1. 10.2.1.2.4.1 Input Capacitor
            2. 10.2.1.2.4.2 Output Capacitor DC-DC Converter
              1. 10.2.1.2.4.2.1 Small Signal Stability
            3. 10.2.1.2.4.3 Output Capacitor LDO
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Low Profile Solution, Maximum Height 1.8 mm
      3. 10.2.3 Dual Power Supply With Auxiliary Positive Output Voltage
      4. 10.2.4 Dual Power Supply With Auxiliary Negative Output Voltage
      5. 10.2.5 Single Output Using LDO as Filter
      6. 10.2.6 Dual Input Power Supply Solution
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Layout

12.1 Layout Guidelines

As for all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.

The feedback divider should be placed as close as possible to the control ground pin of the device. To lay out the control ground, using short traces is also recommended, separated from the power ground traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and control ground current.

12.2 Layout Example

TPS61120 TPS61121 TPS61122 TPS61120_Layout.gifFigure 32. Layout Example

12.3 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are listed below.

  • Improving the power dissipation capability of the PCB design
  • Improving the thermal coupling of the component to the PCB
  • Introducing airflow in the system

The maximum junction temperature (TJ) of the TPS6112x devices is 150 °C. The thermal resistance of the 16-pin TSSOP package (PW) is RΘJA = 100.5°C/W. The 16-pin QFN (RSA) has a thermal resistance of RΘJA = 33.9°C/W, if the thermal pad is soldered and the board layout is optimized. Specified regulator operation is assured to a maximum ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about 647 mW for the TSSOP (PW) package and 1917 mW for the QFN (RSA) package; see Equation 10. More power can be dissipated if the maximum ambient temperature of the application is lower.

Equation 10. TPS61120 TPS61121 TPS61122 Q_PDMAX_LVS427.gif

If designing for a lower junction temperature of 125°C, which is recommended, maximum heat dissipation is lower. Using the above Equation 10 results in 1180 mW power dissipation for the RSA package and 400 mW for the PW package.