SLVSAX2B September   2011  – June 2020 TPS61170-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Soft Start-up
      2. 7.3.2 Overcurrent Protection
      3. 7.3.3 Undervoltage Lockout
      4. 7.3.4 Thermal Shutdown
      5. 7.3.5 Enable and Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Program Mode
      2. 7.4.2 1-Wire Program Mode
      3. 7.4.3 EasyScale
    5. 7.5 Programming
      1. 7.5.1 Feedback Reference Program Mode Selection
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 12-V to 24-V DC-DC Power Conversion
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Program Output Voltage
          2. 8.2.1.2.2 Maximum Output Current
          3. 8.2.1.2.3 Switch Duty Cycle
          4. 8.2.1.2.4 Inductor Selection
          5. 8.2.1.2.5 Schottky Diode Selection
          6. 8.2.1.2.6 Compensation Capacitor Selection
          7. 8.2.1.2.7 Input and Output Capacitor Selection
        3. 8.2.1.3 Application Curve
      2. 8.2.2 5-V to 12-V DC-DC Power Conversion With Programmable Feedback Reference Voltage
      3. 8.2.3 12-V SEPIC (Buck-Boost) Converter
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.3 EasyScale

EasyScale is a simple but very flexible 1-pin interface to configure the FB voltage. The interface is based on a master-slave structure, where the master is typically a microcontroller or application processor. Figure 12 and Table 2 give an overview of the protocol. The protocol consists of a device-specific address byte and a data byte. The device-specific address byte is fixed to 72 hex. The data byte consists of 5 bits for information, 2 address bits, and the RFA bit. The RFA bit set to high indicates the Request for Acknowledge condition. The Acknowledge condition is only applied if the protocol was received correctly. The advantage of EasyScale compared with other on pin interfaces is that its bit detection is in a large extent independent from the bit transmission rate. EasyScale can automatically detect bit rates from 1.7 kbsp up to 160 kbsp.

Table 2. Selectable FB Voltage

FB VOLTAGE (mV) D4 D3 D2 D1 D0
0 0.000 0 0 0 0 0
1 0.031 0 0 0 0 1
2 0.049 0 0 0 1 0
3 0.068 0 0 0 1 1
4 0.086 0 0 1 0 0
5 0.104 0 0 1 0 1
6 0.123 0 0 1 1 0
7 0.141 0 0 1 1 1
8 0.160 0 1 0 0 0
9 0.178 0 1 0 0 1
10 0.197 0 1 0 1 0
11 0.215 0 1 0 1 1
12 0.234 0 1 1 0 0
13 0.270 0 1 1 0 1
14 0.307 0 1 1 1 0
15 0.344 0 1 1 1 1
16 0.381 1 0 0 0 0
17 0.418 1 0 0 0 1
18 0.455 1 0 0 1 0
19 0.492 1 0 0 1 1
20 0.528 1 0 1 0 0
21 0.565 1 0 1 0 1
22 0.602 1 0 1 1 0
23 0.639 1 0 1 1 1
24 0.713 1 1 0 0 0
25 0.787 1 1 0 0 1
26 0.860 1 1 0 1 0
27 0.934 1 1 0 1 1
28 1.008 1 1 1 0 0
29 1.082 1 1 1 0 1
30 1.155 1 1 1 1 0
31 1.229 1 1 1 1 1
TPS61170-Q1 scale_lvs789.gifFigure 12. EasyScale Protocol Overview

Table 3. EasyScale Bit Description

BYTE BIT NUMBER NAME TRANSMISSION DIRECTION DESCRIPTION
Device Address Byte
72 hex		 7 DA7 IN 0 MSB device address
6 DA6 1
5 DA5 1
4 DA4 1
3 DA3 0
2 DA2 0
1 DA1 1
0 DA0 0 LSB device address
Data byte 7 (MSB) RFA IN Request for acknowledge. If high, acknowledge is applied by device
6 A1 0 Address bit 1
5 A0 0 Address bit 0
4 D4 Data bit 4
3 D3 Data bit 3
2 D2 Data bit 2
1 D1 Data bit 1
0 (LSB) D0 Data bit 0
ACK OUT Acknowledge condition active 0, this condition will only be applied if the RFA bit is set. Open-drain output, Line must be pulled high by the host with a pullup resistor. This feature can only be used if the master has an open-drain output stage. In case of a push-pull output stage Acknowledge condition may not be requested!
TPS61170-Q1 bit_coding_lvs789.gifFigure 13. EasyScale — Bit Coding

All bits are transmitted MSB first and LSB last. Figure 13 shows the protocol without acknowledge request (bit RFA = 0), Figure 13 with acknowledge (bit RFA = 1) request. Before both bytes, device address byte and data byte, a start condition must be applied. For this, the CTRL pin must be pulled high for at least tstart (2 μs) before the bit transmission starts with the falling edge. If the CTRL pin is already at high level, no start condition is needed before the device address byte. The transmission of each byte is closed with an End of Stream condition for at least tEOS (2 μs).

The bit detection is based on a Logic Detection scheme, where the criterion is the relation between tLOW and tHIGH. It can be simplified to:

High bit: tHIGH > tLOW, but with tHIGH at least 2x tLOW, see Figure 13.

Low bit: tHIGH < tLOW, but with tLOW at least 2x tHIGH, see Figure 13.

The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending on the relation between tHIGH and tLOW, the logic 0 or 1 is detected.

The acknowledge condition is only applied if:

  • Acknowledge is requested by a set RFA bit.
  • The transmitted device address matches with the device address of the device.
  • 16 bits are received correctly.

If the device turns on the internal ACKN-MOSFET and pulls the CTRL pin low for the time tACKN, which is 512 μs maximum then the Acknowledge condition is valid after an internal delay time tvalACK. This means that the internal ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was detected. The master controller keeps the line low in this period. The master device can detect the acknowledge condition with its input by releasing the CTRL pin after tvalACK and read back a logic 0. The CTRL pin can be used again after the acknowledge condition ends.

The Acknowledge condition may only be requested if the master device has an open-drain output. For the push-pull output stage, the use a series resistor in the CRTL line to limit the current to 500 μA is recommended for such cases as:

  • An accidentally requested acknowledge
  • To protect the internal ACKN-MOSFET