SLVSAX2B September 2011 – June 2020 TPS61170-Q1
PRODUCTION DATA.
The TPS61170-Q1 integrates a 40-V low-side FET for providing output voltages up to 38 V. The device regulates the output with current mode PWM (pulse width modulation) control. The switching frequency of the PWM is fixed at 1.2 MHz (typical). The PWM control circuitry turns on the switch at the beginning of each switching cycle. The input voltage is applied across the inductor and stores the energy as the inductor current ramps up. During this portion of the switching cycle, the load current is provided by the output capacitor. When the inductor current rises to the threshold set by the error amplifier output, the power switch turns off and the external Schottky diode is forward biased. The inductor transfers stored energy to replenish the output capacitor and supply the load current. This operation repeats each switching cycle. As shown in the block diagram, the duty cycle of the converter is determined by the PWM control comparator which compares the error amplifier output and the current signal.
A ramp signal from the oscillator is added to the current ramp. This slope compensation ramp is necessary to avoid subharmonic oscillations that are intrinsic to current mode control at duty cycles higher than 50%. The feedback loop regulates the FB pin to a reference voltage through an error amplifier. The output of the error amplifier must be connected to the COMP pin. An external RC compensation network must be connected to the COMP pin to optimize the feedback loop for stability and transient response.