8.3.1 Soft Start-Up

Soft-start circuitry is integrated into the IC to avoid a high inrush current during start-up. After the device is enabled by a logic high signal on the CTRL pin, the FB pin reference voltage ramps up in 32 steps, with each step taking 213 μs. This ensures that the output voltage rises slowly to reduce inrush current. Additionally, for the first 5 msec after the COMP voltage ramps, the current limit of the PWM switch is set to half of the normal current limit specification or below 700 mA (typical). See the start-up waveform for a typical example, Figure 16.

8.3.2 Overcurrent Protection

TPS61170 has a cycle-by-cycle overcurrent limit feature that turns off the power switch once the inductor current reaches the overcurrent limit. The PWM circuitry resets itself at the beginning of the next switch cycle. During an over-current event, this results in a decrease of output voltage that is directly proportional to load current. The current limit threshold as well as input voltage, output voltage, switching frequency and inductor value determine the maximum available output current. Larger inductance values typically increase the current output capability because of the reduced current ripple. See Maximum Output Current for the output current calculation.

8.3.3 Undervoltage Lockout (UVLO)

An undervoltage lockout prevents mis-operation of the device at input voltages below 2.2 V (typical). When the input voltage is below the undervoltage threshold, the device remains off and the internal switch FET is turned off. The undervoltage lockout threshold is set below minimum operating voltage of 3V to avoid any transient VIN dip triggering the UVLO and causing the device to reset. For the input voltages between UVLO threshold and 3 V, the device attempts operation, but the specifications are not ensured.

8.3.4 Thermal Shutdown

An internal thermal shutdown turns off the device when the typical junction temperature of 160°C is exceeded. The IC restarts when the junction temperature drops by 15°C.

8.3.5 Enable and Shutdown

The TPS61170 enters shutdown when the CTRL voltage is less than 0.4 V for more than 2.5 ms. In shutdown, the input supply current for the device is less than 1 μA (maximum). The CTRL pin has an internal 800-kΩ (typical) pulldown resistor to disable the device when the pin is left unconnected.

8.4.1 Feedback Reference Program Mode Selection

The CTRL pin is used for changing the FB pin reference voltage on-the-fly. There are two methods to program the reference voltage, PWM signal and 1-wire interface (EasyScale). The programming mode is selected each time the device is enabled. The default mode is to use the duty cycle of the PWM signal on the CTRL pin to modulate the reference voltage. To enter the 1-wire interface mode, the following digital pattern on the CTRL pin must be recognized by the IC every time the IC starts from the shutdown mode.

1. Pull CTRL pin high to enable the TPS61170 and to start the 1 wire mode detection window.
2. After the EasyScale detection delay (t_{es_delay}, 100 μsec) expires, drive CTRL low for more than the EasyScale detection time (t_{es_detect}, 260 μsec).
3. The CTRL pin has to be low for more than EasyScale detection time before the EasyScale detection window (t_{es_win}, 1msec) expires. EasyScale detection window starts from the first CTRL pin low to high transition.

The IC immediately enters the 1-wire mode once the previous three conditions are met. The EasyScale communication can start before the detection window expires. Once the mode is programmed, it can not be changed without another start up. In other words, the IC must be shutdown by pulling the CTRL low for 2.5 ms and restarted in order to exit EasyScale Mode. See Figure 8 for a graphical explanation.

Figure 8. Mode Detection of Feedback Reference Program

8.4.2 PWM Program Mode

When the CTRL pin is constantly high, the FB voltage is regulated to 1.229V typically. However, the CTRL pin allows a PWM signal to lower this regulation voltage. The relationship between the duty cycle and FB voltage is given in Equation 1:

As shown in Figure 9, the IC chops up the internal 1.229 V reference voltage at the duty cycle of the PWM signal. The pulse signal is then filtered by an internal low pass filter. The output of the filter is connected to the error amplifier as the reference voltage for the FB pin regulation. The regulation voltage is independent of the PWM logic voltage level which often has large variations.

For optimum performance, use the PWM mode in the range of 5 kHz to 100 kHz. The requirement of minimum frequency comes from the EasyScale detection delay and detection time specification for the mode selection. The device can mistakenly enter 1 wire mode if the PWM signal frequency is less than 5 kHz. Because there is an internal fixed ON-time error of 40 nS, the FB voltage absolute value will be different than expected when the PWM frequency is above 100 kHz. For example, the additional duty cycle of 3.2% due to the ON-time error increases the FB voltage when using an 800 kHz PWM signal. A compromise between PWM frequency and FB voltage accuracy extends the frequency range. Adding an external RC filter to the pin serves no purpose.

Figure 9. Block Diagram of Programmable FB Voltage Using PWM Signal

8.4.3 1-Wire Program Mode

The CTRL pin features a simple digital interface to control the feedback reference voltage. The 1-wire mode can save the processor power and battery life as it does not require a PWM signal all the time, and the processor can enter idle mode if available.

The TPS61170 adopts the EasyScale protocol, which can program the FB voltage to any of the 32 steps with single command. See Table 2 for the FB pin voltage steps. The programmed reference voltage is stored in an internal register. The default value is full scale when the device is first enabled (V_FB = 1.229 V). A power reset clears the register value and reset it to default.

8.5.1 EasyScale

EasyScale is a simple but very flexible one pin interface to configure the FB voltage. The interface is based on a master-slave structure, where the master is typically a microcontroller or application processor. Figure 10 and Table 2 give an overview of the protocol. The protocol consists of a device specific address byte and a data byte. The device specific address byte is fixed to 72 hex. The data byte consists of five bits for information, two address bits, and the RFA bit. The RFA bit set to high indicates the Request for Acknowledge condition. The Acknowledge condition is only applied if the protocol was received correctly. The advantage of EasyScale compared with other on pin interfaces is that its bit detection is in a large extent independent from the bit transmission rate. It can automatically detect bit rates between 1.7 kBit/sec and up to 160 kBit/sec.

Figure 10. EasyScale Protocol Overview

Figure 11. EasyScale— Bit Coding

All bits are transmitted MSB first and LSB last. Figure 11 shows the protocol without acknowledge request (Bit RFA = 0), Figure 11 with acknowledge (Bit RFA = 1) request. Prior to both bytes, device address byte and data byte, a start condition must be applied. For this, the CTRL pin must be pulled high for at least t_start (2 μs) before the bit transmission starts with the falling edge. If the CTRL pin is already at high level, no start condition is needed prior to the device address byte. The transmission of each byte is closed with an End of Stream condition for at least t_EOS (2 μs).

The bit detection is based on a Logic Detection scheme, where the criterion is the relation between t_LOW and t_HIGH. It can be simplified to:

High Bit: t_HIGH > t_LOW, but with t_HIGH at least 2x t_LOW, see Figure 11.

Low Bit: t_HIGH < t_LOW, but with t_LOW at least 2x t_HIGH, see Figure 11.

The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending on the relation between t_HIGH and t_LOW, the logic 0 or 1 is detected.

The acknowledge condition is only applied if:

• Acknowledge is requested by a set RFA bit.
• The transmitted device address matches with the device address of the device.
• 16 bits is received correctly.

If the device turns on the internal ACKN-MOSFET and pulls the CTRL pin low for the time t_ACKN, which is 512 μs maximum then the Acknowledge condition is valid after an internal delay time t_valACK. This means that the internal ACKN-MOSFET is turned on after t_valACK, when the last falling edge of the protocol was detected. The master controller keeps the line low in this period. The master device can detect the acknowledge condition with its input by releasing the CTRL pin after t_valACK and read back a logic 0. The CTRL pin can be used again after the acknowledge condition ends.

Note that the acknowledge condition may only be requested if the master device has an open-drain output. For the push-pull output stage, the use a series resistor in the CRTL line to limit the current to 500 μA is recommended for such cases as:

• an accidentally requested acknowledge, or
• to protect the internal ACKN-MOSFET.