SLVSCN9B December   2014  – June 2020 TPS61175-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Switching Frequency
      2. 7.3.2 Soft Start
      3. 7.3.3 Overcurrent Protection
      4. 7.3.4 Enable and Thermal Shutdown
      5. 7.3.5 Under Voltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Minimum ON Time and Pulse Skipping
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Determining the Duty Cycle
        2. 8.2.2.2 Selecting the Inductor
        3. 8.2.2.3 Computing the Maximum Output Current
        4. 8.2.2.4 Setting Output Voltage
        5. 8.2.2.5 Setting the Switching Frequency
        6. 8.2.2.6 Setting the Soft Start Time
        7. 8.2.2.7 Selecting the Schottky Diode
        8. 8.2.2.8 Selecting the Input and Output Capacitors
        9. 8.2.2.9 Compensating the Small Signal Control Loop
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Soft Start

The TPS61175-Q1 has a built-in soft start circuit which significantly reduces the start-up current spike and output voltage overshoot. When the IC is enabled, an internal bias current (6-μA typically) charges a capacitor (C3) on the SS pin. The voltage at the capacitor clamps the output of the internal error amplifier that determines the duty cycle of PWM control, thereby the input inrush current is eliminated. Once the capacitor reaches 1.8-V, the soft start cycle is completed and the soft start voltage no longer clamps the error amplifier output. Refer to Figure 7 for the soft start waveform. See Table 2 for C3 and corresponding soft start time. A 47-nF capacitor eliminates the output overshoot and reduces the peak inductor current for most applications.

Table 2. Soft Start Time vs C3

VIN (V) VOUT (V) Load (A) COUT (μF) fSW (MHz) C3 (nF) tSS(ms) Overshot (mV)
5 24 0.4 10 1.2 47 4 none
10 0.8 210
12 35 0.6 10 2 100 6.5 none
10 0.4 300

When the EN is pulled low for 10-ms, the IC enters shutdown and the SS capacitor discharges through a 5kΩ resistor for the next soft start.