SLVSAO4C December   2010  – June 2020 TPS61240-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Limit Operation
      2. 7.3.2 Undervoltage Lockout
      3. 7.3.3 Input Overvoltage Protection
      4. 7.3.4 Enable
      5. 7.3.5 Soft Start
      6. 7.3.6 Load Disconnect
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Save Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programming the Output Voltage
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Input Capacitor
        4. 8.2.2.4 Output Capacitor
        5. 8.2.2.5 Checking Loop Stability
      3. 8.2.3 Application Curves
    3. 8.3 System Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Overview

The TPS61240-Q1 boost converter operates with typically a 3.5-MHz fixed-frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the converter automatically enters Power Save Mode and then operates in pulse frequency modulation (PFM) mode.

During PWM operation the converter uses a unique fast response quasi-constant on-time valley current mode controller scheme, which allows best in class line and load regulation allowing the use of small ceramic input and output capacitors and a small inductor. During shutdown, the load is completely disconnected from the battery.

Based on the VIN/VOUT ratio, a simple circuit predicts the required on-time. At the beginning of the switching cycle, the low-side N-MOS switch is turned-on and the inductor current ramps up to a peak current that is defined by the on-time and the inductance. In the second phase, once the peak current is reached, the current comparator trips and the on-timer is reset and this turns off N-MOS switch. Now rectifier switch (P-MOS) is turned on and the inductor current decays to an internally set valley current threshold. Finally, the switching cycle repeats by setting the on timer again and activating the low-side N-MOS switch.

In general, a DC-to-DC step-up converter can only operate in true boost mode, that is, the output is boosted by a certain amount above the input voltage. The TPS61240-Q1 device operates differently as it can smoothly transition in and out of zero duty-cycle operation. Therefore, the output can be kept as close as possible to its regulation limits even though the converter is subject to an input voltage that tends to be excessive.