SLVSAG8G September   2011  – June 2016 TPS61253 , TPS61254 , TPS61256 , TPS61258 , TPS61259 , TPS612592

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Current Limit Operation
      2. 9.3.2 Enable
      3. 9.3.3 Load Disconnect and Reverse Current Protection
      4. 9.3.4 Softstart
      5. 9.3.5 Undervoltage Lockout
      6. 9.3.6 Thermal Regulation
      7. 9.3.7 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Save Mode
      2. 9.4.2 Standby Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Output Capacitor
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Checking Loop Stability
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Summary
      1. 14.1.1 Package Dimensions

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YFF|9
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Detailed Description

9.1 Overview

The TPS6125x synchronous step-up converter typically operates at a quasi-constant 3.5-MHz frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6125x converter operates in power-save mode with pulse frequency modulation (PFM).

During PWM operation, the converter uses a novel quasi-constant on-time valley current mode control scheme to achieve excellent line/load regulation and allows the use of a small ceramic inductor and capacitors. Based on the VIN/VOUT ratio, a simple circuit predicts the required on-time.

At the beginning of the switching cycle, the low-side N-MOS switch is turned-on and the inductor current ramps up to a peak current that is defined by the on-time and the inductance. In the second phase, once the on-timer has expired, the rectifier is turned-on and the inductor current decays to a preset valley current threshold. Finally, the switching cycle repeats by setting the on timer again and activating the low-side N-MOS switch.

In general, a dc/dc step-up converter can only operate in "true" boost mode, i.e. the output “boosted” by a certain amount above the input voltage. The TPS6125x device operates differently as it can smoothly transition in and out of zero duty cycle operation. Therefore the output can be kept as close as possible to its regulation limits even though the converter is subject to an input voltage that tends to be excessive. In this operation mode, the output current capability of the regulator is limited to ca. 150mA. Refer to Figure 11 for further details.

The current mode architecture with adaptive slope compensation provides excellent transient load response, requiring minimal output filtering. Internal soft-start and loop compensation simplifies the design process while minimizing the number of external components.

9.2 Functional Block Diagram

TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 fbd_lvsag8.gif

9.3 Feature Description

9.3.1 Current Limit Operation

The TPS6125x device employs a valley current limit sensing scheme. Current limit detection occurs during the off-time by sensing of the voltage drop across the synchronous rectifier.

The output voltage is reduced as the power stage of the device operates in a constant current mode. The maximum continuous output current (IOUT(CL)), before entering current limit (CL) operation, can be defined by Equation 1.

Equation 1. TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 eq1_IOUT_DD_lvsag8.gif

The duty cycle (D) can be estimated by Equation 2

Equation 2. TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 eq2_D_DD_lvs956.gif

and the peak-to-peak current ripple (ΔIL) is calculated by Equation 3

Equation 3. TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 eq3_diL_DD_lvs956.gif

The output current, IOUT(DC), is the average of the rectifier ripple current waveform. When the load current is increased such that the lower peak is above the current limit threshold, the off-time is increased to allow the current to decrease to this threshold before the next on-time begins (so called frequency fold-back mechanism). When the current limit is reached the output voltage decreases during further load increase.

Figure 26 illustrates the inductor and rectifier current waveforms during current limit operation.

TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 ind_cur_lvsag8.gif Figure 26. Inductor/Rectifier Currents in Current Limit Operation

9.3.2 Enable

The TPS6125x device starts operation when EN is set high and starts up with the soft-start sequence. For proper operation, the EN pin must be terminated and must not be left floating.

Pulling the EN and BP pins low forces the device in shutdown, with a shutdown current of typically 1 µA. In this mode, true load disconnect between the battery and load prevents current flow from VIN to VOUT, as well as reverse flow from VOUT to VIN.

Pulling the EN pin low and the BP pin high forces the device in standby mode, refer to the Standby Mode section for more details.

9.3.3 Load Disconnect and Reverse Current Protection

Regular boost converters do not disconnect the load from the input supply and therefore a connected battery will be discharged during shutdown. The advantage of TPS6125x is that this converter disconnects the output from the input of the power supply when it is disabled (so called true shutdown mode). In case of a connected battery it prevents it from being discharged during shutdown of the converter.

9.3.4 Softstart

The TPS6125x device has an internal softstart circuit that limits the inrush current during start-up. The first step in the start-up cycle is the pre-charge phase. During pre-charge, the rectifying switch is turned on until the output capacitor is charged to a value close to the input voltage. The rectifying switch is current limited (approximately 200 mA) during this phase. This mechanism is used to limit the output current under short-circuit condition.

Once the output capacitor has been biased to the input voltage, the converter starts switching. The soft-start system progressively increases the on-time as a function of the input-to-output voltage ratio. As soon as the output voltage is reached, the regulation loop takes control and full current operation is permitted.

9.3.5 Undervoltage Lockout

The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and the battery from excessive discharge. It disables the output stage of the converter once the falling VIN trips the under-voltage lockout threshold VUVLO which is typically 2.0V. The device starts operation once the rising VIN trips VUVLO threshold plus its hysteresis of 100 mV at typically 2.1 V.

9.3.6 Thermal Regulation

The TPS6125x device contains a thermal regulation loop that monitors the die temperature during the pre-charge phase. If the die temperature rises to high values of about 110 °C, the device automatically reduces the current to prevent the die temperature from increasing further. Once the die temperature drops about 10 °C below the threshold, the device will automatically increase the current to the target value. This function also reduces the current during a short-circuit condition.

9.3.7 Thermal Shutdown

As soon as the junction temperature, TJ, exceeds 140°C (typ.) the device goes into thermal shutdown. In this mode, the high-side and low-side MOSFETs are turned-off. When the junction temperature falls below the thermal shutdown minus its hysteresis, the device continuous the operation.

9.4 Device Functional Modes

9.4.1 Power Save Mode

The TPS6125x integrates a power save mode to improve efficiency at light load. In power save mode the converter only operates when the output voltage trips below a set threshold voltage.

It ramps up the output voltage with several pulses and goes into power save mode once the output voltage exceeds the set threshold voltage.

The PFM mode is left and PWM mode entered in case the output current can not longer be supported in PFM mode.

TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 pwr_sav_lvsag8.gif Figure 27. Power Save

9.4.2 Standby Mode

The TPS6125x device is able to maintain its output biased at the input voltage level. In so called standby mode (EN = 0, BP = 1), the synchronous rectifier is current limited to ca. 150mA allowing an external load (e.g. audio amplifier) to be powered with a restricted supply. The output voltage is slightly reduced due to voltage drop across the rectifier MOSFET and the inductor DC resistance. The device consumes only a standby current of 21 µA (typ).

Table 2. Operating Mode Control

OPERATING MODE EN BP
Shutdown, True Load Disconnect (SD) 0 0
Standby Mode, Output Pre-Biased (SM) 0 1
Boost Operating Mode (BST) 1 0
1 1