SLVSAG8G September   2011  – June 2016 TPS61253 , TPS61254 , TPS61256 , TPS61258 , TPS61259 , TPS612592

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Current Limit Operation
      2. 9.3.2 Enable
      3. 9.3.3 Load Disconnect and Reverse Current Protection
      4. 9.3.4 Softstart
      5. 9.3.5 Undervoltage Lockout
      6. 9.3.6 Thermal Regulation
      7. 9.3.7 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Save Mode
      2. 9.4.2 Standby Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Output Capacitor
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Checking Loop Stability
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Summary
      1. 14.1.1 Package Dimensions

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YFF|9
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage Voltage at VIN(2), VOUT(2), SW(2), EN(2), BP(2) –0.3 7 V
Input current Continuous average current into SW (4) 1.8 A
Peak current into SW (5) 3.5
Power dissipation Internally limited
Temperature Operating, TA (3) –40 85 °C
Operating virtual junction, TJ –40 150
Storage, Tstg –65 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA(max)= TJ(max)–(θJA X PD(max)). To achieve optimum performance, it is recommended to operate the device with a maximum junction temperature of 105°C.
(4) Limit the junction temperature to 105°C for continuous operation at maximum output power.
(5) Limit the junction temperature to 125°C for 5% duty cycle operation.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
Machine model (MM) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VI Input voltage range TPS61253 2.65(1) 4.85 V
TPS61254 2.5 4.35
TPS61256 2.5 4.85
TPS61257 2.5 4.15
TPS61258 2.65(1) 4.35
TPS61259 2.65(1) 4.85
TPS612592 2.65(1) 4.85
RL Minimum resistive load for start-up TPS6125x 55 Ω
L Inductance 0.7 1.0 2.9 µH
CO Output capacitance 3.5 5 50 µF
TA Ambient temperature –40 85 °C
TJ Operating junction temperature –40 125 °C
(1) Up to 1000mA peak output current.

7.4 Thermal Information

THERMAL METRIC(1) TPS6125x UNIT
YFF
9 PINS
RθJA Junction-to-ambient thermal resistance 108.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 1.0
RθJB Junction-to-board thermal resistance 18
ψJT Junction-to-top characterization parameter 4.2
ψJB Junction-to-board characterization parameter 17.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

Minimum and maximum values are at VIN = 2.3V to 5.5V, EN = 1.8V, TA = –40°C to 85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at VIN = 3.6V, EN = 1.8V, TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IQ Operating quiescent current
into VIN Operating quiescent current
into VOUT Standby mode quiescent current
into VIN Standby mode quiescent current
into VOUT 		IOUT = 0mA, VIN = 3.6V
EN = VIN, BP = GND
Device not switching		 30 45 µA
7 15 µA
IOUT = 0mA, VIN = VOUT = 3.6V
EN = GND, BP = VIN
Device not switching		 11 20 µA
9.5 15 µA
ISD Shutdown current EN = GND, BP = GND 0.85 5.0 μA
VUVLO Under-voltage lockout threshold Falling 2.0 2.1 V
Hysteresis 0.1 V
ENABLE, BYPASS
VIL Low-level input voltage 0.4 V
VIH High-level input voltage 1.0 V
Ilkg Input leakage current Input connected to GND or VIN 0.5 µA
OUTPUT
VOUT Regulated DC output voltage TPS61253 2.3V ≤ VIN ≤ 4.85V, IOUT = 0mA
PWM operation. Open Loop		 4.92 5 5.08 V
3.3V ≤ VIN ≤ 4.85V, 0mA ≤ IOUT ≤ 1000mA
PFM/PWM operation		 4.85 5 5.2
3.3V ≤ VIN ≤ 4.85V, 0mA ≤ IOUT ≤ 1500mA
PFM/PWM operation
Pulsed load test; Pulse width ≤ 20ms; Duty cycle ≤ 10%		 4.75 5 5.2
Regulated DC output voltage TPS61254 2.3V ≤ VIN ≤ 4.35V, IOUT = 0mA
PWM operation. Open Loop		 4.43 4.5 4.57 V
2.65V ≤ VIN ≤ 4.35V, 0mA ≤ IOUT ≤ 800mA
PFM/PWM operation		 4.4 4.5 4.65
Regulated DC output voltage TPS61256 2.3V ≤ VIN ≤ 4.85V, IOUT = 0mA
PWM operation. Open Loop		 4.92 5 5.08 V
2.65V ≤ VIN ≤ 4.85V, 0mA ≤ IOUT ≤ 700mA
PFM/PWM operation		 4.9 5 5.2
Regulated DC output voltage TPS61257 2.3V ≤ VIN ≤ 4.15V, IOUT = 0mA
PWM operation. Open loop.		 4.23 4.3 4.37 V
2.65V ≤ VIN ≤ 4.15V, 0mA ≤ IOUT ≤ 800mA
PFM/PWM operation		 4.2 4.3 4.45
Regulated DC output voltage TPS61258 2.3V ≤ VIN ≤ 4.35V, IOUT = 0mA
PWM operation. Open Loop		 4.43 4.5 4.57 V
3.3V ≤ VIN ≤ 4.35V, 0mA ≤ IOUT ≤ 1500mA
PFM/PWM operation
Pulsed load test; Pulse width ≤ 20ms; Duty cycle ≤ 10%		 4.3 4.5 4.65
Regulated DC output voltage TPS61259 2.3V ≤ VIN ≤ 4.85V, IOUT = 0mA
PWM operation. Open Loop		 5.02 5.1 5.18 V
3.4V ≤ VIN ≤ 4.85V, 0mA ≤ IOUT ≤ 1500mA
PFM/PWM operation
Pulsed load test; Pulse width ≤ 20ms; Duty cycle ≤ 10%		 4.75 5.1 5.3
Regulated DC output voltage TPS612592 2.7V ≤ VIN ≤ 4.8V, IOUT = 0mA
PWM operation. Open Loop		 5.1 5.2 5.3 V
ΔVOUT Power-save mode output ripple voltage TPS61254
TPS61258		 PFM operation, IOUT = 1mA 45 mVpk
Standby mode output ripple voltage EN = GND, BP = VIN, IOUT = 0mA 80
PWM mode output ripple voltage PWM operation, IOUT = 200mA 20
Power-save mode output ripple voltage TPS61253
TPS61256
TPS61259
TPS612592		 PFM operation, IOUT = 1mA 50 mVpk
Standby mode output ripple voltage EN = GND, BP = VIN, IOUT = 0mA 80
POWER SWITCH
rDS(on) High-side MOSFET on resistance 170 mΩ
Low-side MOSFET on resistance 100
Ilkg Reverse leakage current into VOUT EN = GND, BP = GND 3.5 µA
ILIM Switch valley current limit TPS61253
TPS61258
TPS61259
TPS612592		 EN = VIN, BP = GND. Open Loop 3300 3620 3900 mA
TPS61254
TPS61256
TPS61257		 EN = VIN, BP = GND. Open Loop 1900 2150 2400
Pre-charge mode current limit
(linear mode)		 EN = GND, BP = VIN 165 215 265 mA
Overtemperature protection 140 °C
Overtemperature hysteresis 20 °C
OSCILLATOR
fOSC Oscillator frequency VIN = 3.6V VOUT = 4.5V 3.5 MHz
TIMING
Start-up time TPS6125x BP = GND, IOUT = 0mA.
Time from active EN to start switching		 70 µs
TPS61253
TPS61254
TPS61256
TPS61258
TPS61259
TPS612592		 BP = GND, IOUT = 0mA.
Time from active EN to VOUT 		400 µs

7.6 Typical Characteristics

Table 1. Table of Graphs

FIGURE
η Efficiency vs Output current Figure 1, Figure 2, Figure 3, Figure 5
vs Input voltage Figure 4
VO DC output voltage vs Output current Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 14
vs Input voltage Figure 11
IO Maximum output current vs Input voltage Figure 12, Figure 13
ΔVO Peak-to-peak output ripple voltage vs Output current Figure 15, Figure 16, Figure 17
ICC Supply current vs Input voltage Figure 18, Figure 19
ILIM DC pre-charge current vs Differential input-output voltage Figure 20, Figure 21
Valley current limit vs Temperature Figure 22, Figure 23
rDS(on) MOSFET rDS(on) vs Temperature Figure 24
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc_new3_lvsag8.gif Figure 1. Efficiency vs Output Current
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc4a_lvsag8.gif Figure 2. Efficiency vs Output Current
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 eff_io2a_lvsag8.gif Figure 3. Efficiency vs Output Current
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc6a_lvsag8.gif Figure 5. Efficiency vs Output Current
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc8a_lvsag8.gif Figure 7. DC Output Voltage vs Output Current
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc6ab_lvsag8.gif Figure 9. DC Output Voltage vs Output Current
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc7a_lvsag8.gif Figure 11. DC Output Voltage vs Input Voltage
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 max2_io_vi_lvsag8.gif Figure 13. Maximum Output Current vs Input Voltage
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc16a_lvsag8.gif Figure 15. Peak-to-Peak Output Ripple Voltage vs Output Current
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 outrip_io_lvsag8.gif Figure 17. Peak-to-Peak Output Ripple Voltage vs Output Current
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc17_lvsag8.gif Figure 19. Supply Current vs Input Voltage
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc12_lvsag8.gif Figure 21. DC Pre-Charge Current vs Differential Input-Output Voltage
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 samp_ILIM_lvsag8.gif Figure 23. Valley Current Limit
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc4ab_lvsag8.gif Figure 4. Efficiency vs Input Voltage
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc_new7_lvsag8.gif Figure 6. DC Output Voltage vs Output Current
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc_new9_lvsag8.gif Figure 8. DC Output Voltage vs Output Current
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc12a_voio_lvsag8.gif Figure 10. DC Output Voltage vs Output Current
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc8ab_lvsag8.gif Figure 12. Maximum Output Current vs Input Voltage
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc15_lvsag8.gif Figure 14. DC Output Voltage vs Output Current
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc9b1_lvsag8.gif Figure 16. Peak-to-Peak Output Ripple Voltage vs Output Current
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc10_lvsag8.gif Figure 18. Supply Current vs Input Voltage
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc11_lvsag8.gif Figure 20. DC Pre-Charge Current vs Differential Input-Output Voltage
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc18_lvsag8.gif Figure 22. Valley Current Limit
TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592 tc14_lvsag8.gif Figure 24. MOSFET rDS(on) vs Temperature