SLVSEA0B
january 2018 – june 2023
TPS61280D
,
TPS61280E
,
TPS61281D
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Device Comparison Table
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
I2C Interface Timing Characteristics #GUID-BD85FD7C-B9AF-4F5D-9DFF-CD61365A592A/SLVS5401494
8.7
I2C Timing Diagrams
8.8
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Voltage Scaling Management (VSEL)
9.3.2
Spread Spectrum, PWM Frequency Dithering
9.4
Device Functional Modes
9.4.1
Power-Save Mode
9.4.2
Pass-Through Mode
9.4.3
Mode Selection
9.4.4
Current Limit Operation
9.4.5
Start-Up and Shutdown Mode
9.4.6
Undervoltage Lockout
9.4.7
Thermal Shutdown
9.4.8
Fault State and Power-Good
9.5
Programming
9.5.1
Serial Interface Description (TPS61280D/E)
9.5.2
Standard-, Fast-, Fast-Mode Plus Protocol
9.5.3
HS-Mode Protocol
9.5.4
TPS6128xD/E I2C Update Sequence
9.6
Register Maps
9.6.1
Slave Address Byte
9.6.2
Register Address Byte
9.6.3
I2C Registers, E2PROM, Write Protect
9.6.4
E2PROM Configuration Parameters
9.6.5
CONFIG Register [reset = 0x01]
9.6.6
VOUTFLOORSET Register [reset = 0x02]
9.6.7
VOUTROOFSET Register [reset = 0x03]
9.6.8
ILIMSET Register [reset = 0x04]
9.6.9
Status Register [reset = 0x05]
9.6.10
E2PROMCTRL Register [reset = 0xFF]
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
TPS61281D with 2.5V-4.35 VIN, 1500 mA Output Current (TPS61280D with default I2C Configuration)
10.2.1.1
Design Requirement
10.2.1.2
Detailed Design Parameters
10.2.1.2.1
Inductor Selection
10.2.1.2.2
Output Capacitor
10.2.1.2.3
Input Capacitor
10.2.1.2.4
Checking Loop Stability
10.2.1.3
Application Performance Curves
10.2.2
TPS61282D with 2.5V-4.35 VIN, 2000 mA Output Current (TPS61280D with I2C Programmable)
10.2.2.1
Design Requirements
10.2.2.2
Detailed Design Procedures
10.2.2.3
Application Performance Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
12.3
Thermal Information
13
Device and Documentation Support
13.1
Device Support
13.1.1
Third-Party Products Disclaimer
13.2
Receiving Notification of Documentation Updates
13.3
Support Resources
13.4
Trademarks
13.5
Electrostatic Discharge Caution
13.6
Glossary
14
Mechanical, Packaging, and Orderable Information
14.1
Package Summary
Package Options
Mechanical Data (Package|Pins)
YFF|16
MXBG096W
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slvsea0b_oa
slvsea0b_pm
1
Features
95% efficiency at 2.3 MHz operation
3-µA quiescent current in low I
Q
pass-through mode
Wide V
IN
range from 2.3 V To 4.8 V
I
OUT
≥ 4-A (Peak) at V
OUT
= 3.35 V, V
IN
≥ 2.65 V
Integrated pass-through mode (35 mΩ)
Programmable valley inductor current limit and output voltage
True pass-through mode during shutdown
Best-in-class
line and load transient
Low-ripple light-load PFM mode
In-Situ customization with On-Chip E
2
PROM (write protection)
Two interface options:
I
2
C compatible I/F up to 3.4 Mbps (TPS61280D/E)
Simple I/O logic control interface
Thermal shutdown and overload protection
Total solution size < 20 mm
2
, sub 1-mm profile