SLVS977B February 2010 – July 2016 TPS61325
PRODUCTION DATA.
The TPS6132x family employs a 2-MHz fixed ON-time, PWM current-mode converter to generate the output voltage required to drive up to three high power LEDs in parallel. The device integrates a power stage based on an NMOS switch and a synchronous PMOS rectifier. The device also implements a set of linear low-side current regulators to control the LED current when the battery voltage is higher than the diode forward voltage.
A special circuit is applied to disconnect the load from the battery during shutdown of the converter. In conventional synchronous rectifier circuits, the back-gate diode of the high-side PMOS is forward biased in shutdown and allows current flowing from the battery to the output. This device however uses a special circuit which takes the cathode of the back-gate diode of the high-side PMOS and disconnects it from the source when the regulator is in shutdown (HC_SEL = L).
The TPS6132x device cannot only operate as a regulated current source but also as a standard voltage boost regulator featuring power-save mode for improved efficiency at light load. Voltage mode operation can be enabled and disabled by software control.
The TPS6132x device also supports storage capacitor on its output (energy storage mode). In this operating mode (HC_SEL = H), the inductive power stage is used to charge-up the super-capacitor to a user selectable value. Once the charge-up is complete, the LEDs can be fired up to 1025 mA (LED1 and LED3) and 2050 mA (LED2) without causing a battery overload.
In general, a boost converter only regulates output voltages which are higher than the input voltage. This device operates differently. For example, in the voltage mode operation the device is capable to regulate 4.2 V at the output from a battery voltage pulsing as high 5.5 V. To control these applications properly, a down conversion mode is implemented.
If the input voltage reaches or exceeds the output voltage, the converter changes to a down conversion mode. In this mode, the control circuit changes the behavior of the rectifying PMOS. It sets the voltage drop across the PMOS as high as required to regulate the output voltage. This means the power losses in the converter increase. This must be taken into account for thermal consideration.
In direct drive mode (HC_SEL = L), the power stage is capable of supplying a maximum total current of roughly 1300 mA to 1500 mA. The TPS6132x provides three constant current inputs capable of sinking up to 445 mA (LED1 and LED3) and 890 mA (LED2) in flashlight mode.
The TPS6132x integrates an I2C compatible interface allowing transfers up to 3.4 Mbps. This communication interface can be used to set the operating mode (shutdown, constant output current mode vs constant output voltage mode), to control the brightness of the external LED (DC-light and flashlight modes), to adjust the output voltage (from 3.825 V to 5.7 V in 125-mV steps) or to program the safety timer for instance. See Register Maps for more details.
In the TPS6132x device, the DC-light and flash can be controlled either by the I2C interface or by the means of hardware control signals (STRB0 and STRB1). The maximum duration of the flashlight pulse can be limited by means of an internal user programmable safety timer (STIM). To avoid the LEDs to be kept accidentally on in DC-light mode by software control, the device implements a 13-s watchdog timer. The DC-light watchdog timer can be disabled by pulling the STRB1 signal high.
The TPS6132x device uses LED forward voltage sensing circuitry on LEDx pins to optimize the power stage boost ratio for maximum efficiency. TI recommends against leaving any of the LEDx pins unused if the operation is selected through ENDLED[3:1] bits due to the nature of the sensing circuitry. Leaving these pins unconnected, whilst the respective ENLEDx bits have been set, forces the control loop into high gain and eventually trip the output over-voltage protection.
The LEDx inputs may be connected together to drive one or two LEDs at higher currents. Connecting the current sink inputs in parallel does not affect the internal operation of the TPS6132x. TI recommends disabling the LED inputs that are not used for best operation (see REGISTER5 (address = 0x05)).
To achieve smooth LED current waveforms, the TPS6132x device actively controls the LED current ramp-up and ramp-down sequences.
DIRECT DRIVE MODE (HC_SEL = 0) | HIGH-CURRENT MODE (HC_SEL = 1) | |
---|---|---|
LED CURRENT RAMP-UP | ISTEP = 27.5 mA | ISTEP = 62 mA |
tRISE = 12 μs | tRISE = 0.5 μs | |
Slew-rate ≈ 2.3 mA/μs | Slew-rate ≈ 124 mA/μs | |
LED CURRENT RAMP-DOWN | ISTEP = 27.5 mA | ISTEP = 62 mA |
tFALL = 0.5 μs | tFALL = 0.5 μs | |
Slew-rate ≈ 55 mA/μs | Slew-rate ≈ 124 mA/μs |
In high-current mode (HC_SEL = 1), the LED current settings are defined as a fixed ratio (×2.25) versus the direct drive mode values (HC_SEL = L).
The LED strobe timer uses the internal oscillator as a reference clock. The timer execution speed (see REGISTER3 (address = 0x03)) scales according to the reference clock accuracy.
OSCILLATOR FREQUENCY | SAFETY TIMER DURATION |
---|---|
Minimum | Maximum = Typical × (1 + fACC)(1) |
Typical | Typical(2) |
Maximum | Minimum = Typical × (1 - fACC)(1) |
The current limit circuit employs a valley current sensing scheme. Current limit detection occurs during the off-time through sensing of the voltage drop across the synchronous rectifier. The detection threshold is user selectable through the ILIM bit. The ILIM bit can only be set while still in shutdown before the device begins operation..
Figure 32 illustrates the inductor and rectifier current waveforms during current limit operation. The output current (IOUT) is the average of the rectifier ripple current waveform. When the load current is increased such that the lower peak is above the current limit threshold, the off-time is lengthened to allow the current to decrease to this threshold before the next on-time begins, so called frequency fold-back mechanism.
Both the output voltage and the switching frequency are reduced as the power stage of the device operates in a constant current mode. Equation 1 shows the maximum continuous output current (IOUT(CL)) before entering current limit operation.
The TPS6132x device also provides a negative current limit (approximately 300 mA) to prevent an excessive reverse inductor current when the power stage sinks current from the output (storage capacitor) in the forced continuous conduction mode.
NOTE
To minimize the requirements on the energy storage capacitor present at the output of the driver (HC_SEL = 1), the TPS6132x device can contribute to a larger extent in supporting directly the high-current LED flash strobe. In fact, the device can dynamically adjust it’s current limit setting according to the Tx-MASK input.
VALLEY CURRENT LIMIT SETTING | ILIM BIT | HC_SEL INPUT | Tx-MASK INPUT |
---|---|---|---|
1150 mA | Low | Low | Low |
1600 mA | High | Low | Low |
30 mA | Low | High | Low |
250 mA | High | High | Low |
1150 mA | Low | Low | High |
1600 mA | High | Low | High |
—(1) | Low | High | High |
—(1) | High | High | High |
To avoid high inrush current during start-up, the internal start-up cycle begins with a precharge phase. During precharge, the rectifying switch is turned on until the output capacitor is either charged to a value close to the input voltage or approximately 3.3 V, whichever occurs first. The rectifying switch is current limited during this phase. The current limit increases with decreasing input to output voltage difference. This circuit also limits the output current under short-circuit conditions at the output. Figure 33 shows the typical precharge current vs input minus the output voltage for a specific input voltage.
In direct drive mode (HC_SEL = L, TPS6132x), after having precharged the output capacitor, the device begins switching and increases its current limit in three steps to the target determined by the ILIM setting, typically to 30 mA, 250 mA, or full current limit. The current limit transition from the first to the second step occurs after a milli-second of operation. Full current limit operation is set once the output voltage reaches its regulation limits. In this mode, the active balancing circuit is disabled.
In high-current mode (HC_SEL = H), the precharge voltage of the storage capacitor is dependent on the input voltage and operating mode (voltage regulation versus current regulation mode). In case the device is set for exclusive current regulation operation (MODE_CTRL = 01 or 10 and ENVM = 0), the output capacitor precharge voltage is close to the input voltage. Under all other operating conditions, the precharge voltage is either close to the input voltage or approximately 3.3 V, whichever is lower. Furthermore, precharge operation can be suspended and resumed through the Tx-MASK input (see REGISTER4 (address = 0x04) and REGISTER3 (address = 0x03)).
The device begins switching after the storage capacitor pre-charging is complete. During down-mode operation, the inductor valley current is actively limited either to 30 mA or 250 mA (see REGISTER4 (address = 0x04)). As the device enters boost mode operation, the current limit transitions to full capacity (see REGISTER4 (address = 0x04) and REGISTER3 (address = 0x03)). As a consequence, the output voltage ramps-up linearly and the start-up time required to reach the programmed output voltage (see REGISTER6 (address = 0x06)) depends primarily on the super-capacitor value and load current. In this mode, the active balancing circuit is enabled.
The TPS6132x integrates a power-good circuitry that is activated when the device is operating in voltage regulation mode (MODE_CTRL = 11 or ENVM = 1). In shutdown mode (MODE_CTRL = 00) the GPIO/PG pin state is defined in Table 5.
GPIOTYPE | GPIO/PG SHUTDOWN STATE |
---|---|
0 | Reset or pulled to ground |
1 | Open-drain |
Depending on the GPIO/PG output stage type selection, push-pull or open-drain, the polarity of the power-good output signal (PG) can be inverted or noninverted. The power-good software bit and hardware signal polarity is defined in Table 6.
GPIOTYPE | PG BIT | GPIO/PG OUTPUT PORT | COMMENTS |
---|---|---|---|
0: push-pull output | 0 | 0 | Output is active high signal polarity |
1 | 1 | ||
1: open-drain output | 0 | Open-drain | Output is active low signal polarity |
1 | Low |
The power good signal is valid when the output voltage is within –1.5% and 2.5% of its nominal value. Conversely, it is asserted low when the voltage mode operation gets suspended (MODE_CTRL ≠ 11 and ENVM = 0).
The TPS6132x device uses a control architecture that allows recycling excessive energy that might be stored in the output capacitor. By reversing the operation of the boost power stage, the converter is able to transfer energy from its output back into the input source. In this case, the power-good signal is deasserted while the output voltage is decreasing towards its target value: the closest fit voltage the converter can support. See Down Mode In Voltage Regulation Mode for additional information.
The TPS6132x devices monitor the LED temperature by measuring the voltage between the TS and AGND pins. An internal current source provides the bias (approximately 24 μA) for a negative-temperature coefficient resistor (NTC), and the TS pin voltage is compared to internal thresholds (1.05 V and 0.345 V) to protect the LEDs against overheating.
The temperature monitoring related blocks are always active in DC-light or flashlight modes. In voltage mode operation (MODE_CTRL = 11), the device only activates the TS input when the ENTS bit is set to high. In shutdown mode, the LED temperature supervision is disabled and the quiescent current of the device is dramatically reduced.
The LEDWARN and LEDHOT bits reflect the LED temperature. The LEDWARN bit is set when the voltage seen at the TS pin is lower than 1.05 V. This threshold corresponds to an LED warning temperature value, the device operation is still permitted.
While regulating LED current (DC-light or flashlight modes), the LEDHOT bit is latched when the voltage seen at the TS pin is lower than 0.345 V. This threshold corresponds to an excessive LED temperature value, the device operation is immediately suspended (MODE_CTRL bits are reset and HOTDIE bits are set).
The hot die detector monitors the junction temperature but does not shutdown the device. It provides an early warning to the camera engine to avoid excessive power dissipation thus preventing thermal shutdown during the next high-power flash strobe.
The hot die detector (HOTDIE bits) reflects the instantaneous junction temperature and is always enabled, except when the device is in shutdown mode (MODE_CTRL = 00).
The undervoltage lockout circuit (UVLO) protects the device from mis-operation at low input voltages by preventing the converter from turning on the switch-MOSFET or rectifier-MOSFET for battery voltages below 2.3 V. The I2C compatible interface is fully functional down to 2.1-V input voltage.
A fully charged super-capacitor typically has a leakage current under 1 μA. The TPS6132x device integrates an active balancing feature to cut the total leakage current from the super-capacitor and balance circuit to less than 1.7 μA (typical).
The device integrates a window comparator to monitor the tap point of the multi-cell super-capacitor. The balancing output (BAL) is substantially half the actual output voltage (VOUT). If the internal leakage current in one capacitor is larger than in the other, the voltage at their junction tends to change in such a way that the voltage on the capacitor with the larger (or largest) leakage current is reduced.
When this happens, current flows from BAL in an appropriate direction to reduce the magnitude of voltage changes. After a long period of steady-state conditions the current from BAL is approximately equal to the difference between the leakage currents of the capacitor pair being balanced by the circuit. The output resistance of the balancing circuit, approximately 250 Ω, determines how quickly an imbalance is corrected.
The TPS6132x device provides a high-side linear constant current source to drive low VF LEDs. The LED current is directly regulated off the battery and can be controlled through the INDC bits. Operation is understood best by referring to the Figure 35 and Figure 36.
The device can provide a path to allow for reverse biasing of white LEDs (see Figure 36). To do so, the output of the converter (VOUT) is pulled to ground thus allowing a reverse current to flow. This mode of operation is only possible when the converter’s power stage is in shutdown (MODE_CTRL = 00, ENVM = 0 and HC_SEL = 0).
The TPS6132x device features white LED drive capability at low light intensity. To generate a reduced LED average current, the device employs a 30-kHz fixed frequency PWM modulation scheme. The PWM timer uses the internal oscillator as reference clock, therefore the PWM modulating frequency shows the same accuracy as the internal reference clock. See Figure 30 for more information on device operation.
The DC-light current is modulated with a duty cycle defined by the INDC bits. The low light dimming mode can only be activated in the software controlled DC-light only mode (MODE_CTRL = 01, ENVM = 1) and applies to the LEDs selected through ENLED bits. In this mode, the DC-light safety timeout feature is disabled.
High-power LEDs tend to exhibit a wide forward voltage distribution. The TPS6132x device integrates a self-calibration procedure that can be used to determine the optimum super-capacitor precharge voltage based on the actual worst case LED forward voltage and ESR of the storage capacitor. This calibration procedure is meant to start at a minimum output voltage and can be initiated by setting the SELFCAL bit, preferably with MODE_CTRL = 00, ENVM = 0.
The calibration procedure monitors the sense voltage across the low-side current regulators, according to ENLED bits setting, and registers the LED featuring the largest forward voltage. The TPS6132x device automatically sweeps through its output voltage range and performs a short duration flash strobe for each step (see REGISTER2 (address = 0x02) and REGISTER1 (address = 0x01)).
In direct drive mode (HC_SEL = L), the energy is being directly transferred from the battery to the LEDs. In high-current mode (HC_SEL = H), the energy is supplied exclusively by the output reservoir capacitor and the inductive power stage is turned off for the flash strobe period of time.
The sequence is stopped once each of the the low-side current regulators has enough headroom voltage, typically 400 mV. The resulting output voltage is written to register OV and the SELFCAL bit is set. The SELFCAL bit is only reset at the start of a calibration cycle. When SELFCAL is asserted, the output voltage register (OV) returns the result of the last calibration sequence.
In high-power LED camera flash applications, the storage capacitor is supposed to be charged to an optimum voltage level to:
High-power LEDs tend to exhibit large dynamic forward voltage variation relating to own self-heating effects. In addition, the energy storage capacitor, an electrochemical double-layer capacitor or super-capacitor, also shows a relatively large effective capacitance and ESR spread. The main factors contributing to these variations are: flash strobe duration, temperature, and ageing effects.
In practice, it normally becomes very challenging to compensate for all these variations and a worst-case design would presumably be too pessimistic. As a consequence, designers would have to give-up on the benefits coming along with the Storage Capacitor, Precharge Voltage Calibration approach.
The TPS6132x device offers the possibility of controlling the storage capacitor precharge voltage in a closed-loop manner. The principle is to dynamically adjust the initial pre-voltage to the minimum value, as required for the particular components characteristic and operating conditions.
The reference criteria used to evaluate proper operation is the headroom voltage across the LED current regulators. In case of a critical headroom voltage (VLEDx) at the end of a flash strobe, cycle n, the precharge voltage must be increased before to the next capture sequence, cycle n + 1.
I2C is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors [1]. The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and transmits data on the bus under control of the master device.
The TPS6132x device works as a slave and supports the following data transfer modes, as defined in the I2C-Bus Specification [1]: standard mode (100 kbps) and fast mode (400 kbps), and high-speed mode (3.4 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as supply voltage remains above 2.1 V.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as HS-mode. The TPS6132x device supports 7-bit addressing; 10-bit addressing and general call address are not supported. The device 7-bit address is defined as ‘011 0011’ (TPS61325) and ‘011 0010’ (TPS61326).
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 40. All I2C-compatible devices must recognize a start condition.
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit (R/W) on the SDA line. The master ensures that data is valid during all transmissions. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 41). All devices receive the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 42) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave is established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver must acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8 data bits and a 1-bit acknowledge can continue as long as necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 40). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address.
The master generates a start condition followed by a valid serial byte containing HS master code 00001xxx. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.
The master then generates a repeated start condition, a repeated start condition has the same timing as the start condition. After this repeated start condition, the protocol is the same as F/S-mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions must be used to secure the bus in HS-mode.
In general, a boost converter only regulates output voltages which are higher than the input voltage. The featured devices come with the ability to regulate 4.2 V at the output with an input voltage as high as 5.5 V. To control these applications properly, a down conversion mode is implemented.
In voltage regulation mode, if the input voltage reaches or exceeds the output voltage, the converter changes to the down-conversion mode. In this mode, the control circuit changes the behavior of the rectifying PMOS. It sets the voltage drop across the PMOS as high as necessary to regulate the output voltage. This means the power losses in the converter increase. This must be taken into account for thermal consideration. The down conversion mode is automatically turned off as soon as the input voltage falls about 200 mV below the output voltage.
For proper operation in down conversion mode the output voltage must not be programmed higher than approximately 5.3 V. Take care not to violate the absolute maximum ratings at the SW pins.
The TPS6132x device uses a control architecture that allows recycling excessive energy that might be stored in the output capacitor. By reversing the operation of the boost power stage, the converter is capable of transferring energy from its output back into the input source.
In high-current mode (HC_SEL = 1), this feature becomes useful to dynamically adjust the output voltage (VOUT) depending on the operating conditions. For example, 4.95 V constant output voltage to support audio applications or variable storage capacitor precharge voltage, see Figure 76.
This reverse operating mode can only perform within an output voltage range higher than the input supply. For example, if the storage capacitor is initially precharged to 4.95 V, the input voltage is around 4.1 V and the target output voltage is set to 3.825 V, the converter is only able to lower the output node down to the input level.
The TPS6132x device integrates a power save mode to improve efficiency at light load. In power save mode the converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with one or several pulses and goes again into power save mode once the output voltage exceeds the set threshold voltage.
The power save mode can be enabled and disabled through the ENPSM bit. In down conversion mode, power save mode is always active and the device cannot be forced into fixed frequency operation at light loads.
The LED sense voltage has a direct effect on the converter’s efficiency. Because the voltage across the low-side current regulator does not contribute to the output power, LED brightness, reducing the sense voltage increases the efficiency of the device.
In direct drive mode (HC_SEL = L), the energy is being directly transferred from the battery to the LEDs. The integrated current control loop automatically selects the minimum boosting ratio to maintain regulation based on the LED forward voltage and current requirements. The low-side current regulators drop the voltage difference between the input voltage and the LEDs forward voltage (VF(LED) < VIN). When running in boost mode (VF(LED) > VIN), the voltage present at the LEDx pins of the low-side current regulators is typically 400 mV, leading to high power conversion efficiency. Depending on the input voltage and the LEDs forward voltage characteristic, the converter shows efficiency in the range of about 75% to 90%.
In high-current mode (HC_SEL = H), the device is only supplying a limited amount of energy directly from the battery, for example, DC-light, contribution to flash current, or voltage regulation mode. During a flash strobe, the bulk of the energy supplied to the LEDs is provided by the reservoir capacitor. The low-side current regulators typically operate with 400-mV headroom voltage. This means the power losses in the device increase and thermal considerations become more important.
Operation is understood best by referring to Figure 30. The device set to one of four different operating modes depending on the state of the MODE_CTRL bits.
In this mode, the high-power LEDs are driven at the flashlight current level and the safety timer (STIM) is running. The maximum duration of the flashlight pulse is defined in the STIM register.
The safety timer is triggered on rising edge and stopped either by a negative logic on the synchronization source (STRB0 = STRB1 = 0) or by a timeout event (TO bit).
In this mode, the high-power LEDs are driven at the flashlight current level and the safety timer (STIM) is running. The duration of the flashlight pulse is defined in the STIM register.
The flashlight strobe is started either by a rising edge on the synchronization source (STRB0 = 1 and STRB1 = 0) or by a positive transition on the START-FLASH/TIMER (SFT) bit (STRB0 = 1 and STRB1 = 0). Once running, the timer ignores all kind of triggering signals and only stops after a timeout (TO). START-FLASH/TIMER (SFT) bit is being reset by the timeout (TO) signal.
If a high-power LED fails as a short circuit, the low-side current regulator limits the maximum output current and the HIGH-POWER LED FAILURE (HPLF) flag is set.
If a high-power LED fails as an open circuit, the control loop initially attempts to regulate off of its low-side current regulator feedback signal. This drives VOUT higher. As the open circuited LED never accepts its programmed current, VOUT must be voltage-limited by means of a secondary control loop.
The TPS6132x device limits VOUT according to the overvoltage protection settings (see Figure 47). In this failure mode, VOUT is either limited to 4.65 V (typical) or 6.0 V (typical) and the HIGH-POWER LED FAILURE (HPLF) flag is set.
OVP THRESHOLD | OPERATING CONDITIONS |
---|---|
4.65 V (typical) | HC_SEL = L and 0000 ≤ OV ≤ 0100 |
6 V (typical) | HC_SEL = H or 0101 ≤ OV ≤ 1111 |
See LED High-current Regulators, Unused Inputs for more information.
The TPS6132x device integrates a software control bit (ENVM) that can be used to force the converter to run in voltage mode regulation. Table 8 gives an overview of the different modes of operation.
INTERNAL REGISTER SETTINGS MODE_CTRL | ENVM | OPERATING MODES |
---|---|---|
00 | 0 | The converter is in shutdown mode and the load is disconnected from the battery. |
01 | 0 | LEDs are turned on for DC-light operation (for example, a movie light). The converter is operating in the current regulation mode (CM). The output voltage is controlled by the forward voltage characteristic of the LED. The energy is being directly transferred from the battery to the output. |
10 | 0 | The converter is operating in the current regulation mode (CM). The output voltage is controlled by the forward voltage characteristic of the LED. LEDs are ready for flashlight operation supported directly from the battery. |
In high-current mode (HC_SEL = H), the energy is supplied by the output reservoir capacitor and the inductive power stage is turned off for the flash strobe period of time. | ||
11 | 0 | LEDs are turned off and the converter is operating in the voltage regulation mode (VM). The output voltage is set through the register OV. |
00 | 1 | LEDs are turned off and the converter is operating in the voltage regulation mode (VM). The output voltage is set through the register OV. |
01 | 1 | The converter is operating in the voltage regulation mode (VM) and the output voltage is set through the register OV. The LED currents are regulated by the low-side current sinks. The LEDs are turned on for DC-light operation and the energy is being directly transferred from the battery to the output. |
10 | 1 | The converter is operating in the voltage regulation mode (VM) and the output voltage is set through the register OV. The LED currents are regulated by the low-side current sinks. The LEDs are ready for flashlight operation. |
In direct drive mode (HC_SEL = L), the energy is being directly transferred from the battery to the output. | ||
In high-current mode (HC_SEL = H), the energy is largely supplied by the output reservoir capacitor. However, the inductive power stage is active, and contributing to the flash power. | ||
11 | 1 | LEDs are turned off and the converter is operating in the voltage regulation mode (VM). The output voltage is set through the register OV. |
In direct drive mode (HC_SEL = 0), the Tx-MASK input signal can be used to disable the flashlight operation, for example, during a RF PA transmission pulse. This blanking function turns the LED from flashlight to DC-light thereby reducing almost instantaneously the peak current loading from the battery. The Tx-MASK function has no influence on the safety timer duration.
In high-current mode (HC_SEL = 1), the Tx-MASK input pin is also used to dynamically adjust the device’s current limit setting, controlling the maximum current drawn from the input source. See Current Limit Operation for additional information.
Pulling the MODE_CTRL bits low forces the device into shutdown, but only if ENVM = 0.
In direct-drive mode (HC_SEL = L) the regulator stops switching, the high-side PMOS disconnects the load from the input, and the LEDx pins are high impedance thus eliminating any DC conduction path. The TPS6132x device actively discharges the output capacitor when it turns off.
The integrated discharge resistor has a typical resistance of 2 kΩ, equally split between VOUT to BAL and BAL to GND outputs. The required time to discharge the output capacitor at VOUT depends on load current and the effective output capacitance. The active balancing circuit is disabled and the device consumes only a shutdown current of 1 μA (typical).
In high-current mode (HC_SEL = H), the device maintains its output biased at the input voltage level. The synchronous rectifier is current limited, for example, precharge current, in this mode, allowing external load, for example, an audio amplifier, to be powered with a restricted supply. The active balancing circuit is enabled and the device consumes only a standby current of 5 μA (typical).
As soon as the junction temperature, TJ, exceeds 160°C (typical), the device goes into thermal shutdown. In this mode, the power stage and the low-side current regulators are turned off, the HOTDIE bits are set and can only be reset by a readout.
In the voltage mode operation (MODE_CTRL = 11 or ENVM = 1), the device continues operation when the junction temperature falls below 140°C (typical) again. In the current regulation mode, DC-light or flashlight modes, the device operation is suspended.
The TPS6132x requires a start condition, a valid I2C address, a register address byte, and a data byte for a single update. After the receiving each byte, the TPS6132x device acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the TPS6132x. The TPS6132x performs an update on the falling edge of the acknowledge signal that follows the LSB byte.
MSB | LSB | ||||||
---|---|---|---|---|---|---|---|
X | X | X | X | X | X | A1 | A0 |
The slave address byte is the first byte received following the START condition from the master device.
MSB | LSB | ||||||
---|---|---|---|---|---|---|---|
0 | 0 | 0 | 0 | 00 | D2 | D1 | D0 |
Following the successful acknowledgement of the slave address, the bus master sends a byte to the TPS6132x, which contains the address of the register to be accessed.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET | FREE | DCLC13 | DCLC2 | ||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-1 | R/W-0 | R/W-1 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D7 | RESET | R/W | 0 |
Register reset 0: Normal operation 1: Default values are set to all internal registers |
D5–D3 | DCLC13 | R/W | 001 |
DC-light current control (LED1 and LED3) 001: 28.0 mA 010: 55.75 mA 011: 83.25 mA 100: 111.0 mA 101: 138.75 mA 110: 166.5 mA 111: 194.25 mA |
D2–D0 | DCLC2 | R/W | 010 |
DC-light current control (LED2) 001: 28.0 mA 010: 55.75 mA 011: 83.25 mA 100: 111.0 mA 101: 138.75 mA 110: 166.5 mA, 249.75 mA current level can be activated simultaneously with Tx‑MASK = 1 111: 194.25 mA, 360.75 mA current level can be activated simultaneously with Tx-MASK = 1 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODE_CTRL | FC2 | ||||||
R/W-0 | R/W-0 | R/W-0 | R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description | |
---|---|---|---|---|---|
D7–D6 | MODE_CTRL | R/W | 00 |
Mode control 00: Device in shutdown mode 01: Device operates in DC-light mode 10: Device operates in flashlight mode 11: Device operates as constant voltage source To avoid device shutdown by DC-light safety timeout, MODE_CTRL bits must be refreshed within less than 13 s. Writing to REGISTER1[7:6] automatically updates REGISTER2[7:6]. |
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D5–D0 | FC2 | R/W | 010000 |
Flash current control (LED2) HC_SEL = 0 000001: 28.0 mA 000010: 55.75 mA 000011: 83.25 mA 000100: 111.0 mA 000101: 138.75 mA 000110: 166.5 mA 000111: 194.25 mA 001000: 222.0 mA 001001: 249.75 mA 001010: 277.5 mA 001011: 305.25 mA 001100: 333.0 mA 001101: 360.75 mA 001110: 388.5 mA 001111: 416.25 mA 010000: 444.0 mA 010001: 471.75 mA 010010: 499.5 mA 010011: 527.25 mA 010100: 555.0 mA 010101: 582.75 mA 010110: 610.5 mA 010111: 638.25 mA 011000: 666.0 mA 011001: 693.75 mA 011010: 721.5 mA 011011: 749.25 mA 011100: 777.0 mA 011101: 804.75 mA 011110: 832.5 mA 011111: 860.25 mA ≥100000: 888.0 mA |
HC_SEL = 1 000001: 64 mA 000010: 130 mA 000011: 196 mA 000100: 260 mA 000101: 324 mA 000110: 388 mA 000111: 452 mA 001000: 516 mA 001001: 580 mA 001010: 644 mA 001011: 708 mA 001100: 772 mA 001101: 836 mA 001110: 900 mA 001111: 964 mA 010000: 1028 mA 010001: 1092 mA 010010: 1156 mA 010011: 1220 mA 010100: 1284 mA 010101: 1348 mA 010110: 1412 mA 010111: 1476 mA 011000: 1540 mA 011001: 1604 mA 011010: 1668 mA 011011: 1732 mA 011100: 1796 mA 011101: 1860 mA 011110: 1924 mA 011111: 1988 mA ≥100000: 2052 mA |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODE_CTRL | ENVM | FC13 | |||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-1 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description | |
---|---|---|---|---|---|
D7–D6 | MODE_CTRL | R/W | 00 |
Mode control 00: Device in shutdown mode 01: Device operates in DC-light mode 10: Device operates in flashlight mode 11: Device operates as constant voltage source To avoid device shutdown by DC-light safety timeout, MODE_CTRL bits must be refreshed within less than 13 s. Writing to REGISTER2[6:5] automatically updates REGISTER1[6:5]. |
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D5 | ENVM | R/W | 0 |
Enable voltage mode 0: Normal operation 1: Forces the device into a constant voltage source In read mode, the ENVM bit returns zero. |
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D4–D0 | FC13 | R/W | 0100 |
Flash current control (LED1 and LED3) HC_SEL = 0 00001: 27.75 mA 00010: 55.5 mA 00011: 83.25 mA 00100: 111.0 mA 00101: 138.75 mA 00110: 166.5 mA 00111: 194.25 mA 01000: 222.0 mA 01001: 249.75 mA 01010: 277.5 mA 01011: 305.25 mA 01100: 333.0 mA 01101: 360.75 mA 01110: 388.5 mA 01111: 416.25 mA ≥10000: 444.0 mA |
HC_SEL = 1 00001: 64.5 mA 00010: 127.0 mA 00011: 192.0 mA 00100: 256.0 mA 00101: 320.25 mA 00110: 384.5 mA 00111: 448.75 mA 01000: 513.0 mA 01001: 577.25 mA 01010: 641.5 mA 01011: 705.75 mA 01100: 770.0 mA 01101: 834.25 mA 01110: 898.5 mA 01111: 962.75 mA ≥10000: 1027.0 mA |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STIM | HPLF | SELSTIM TO |
STT | SFT | Tx-MASK | ||
R/W-1 | R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D7–D5 | STIM | R/W | 110 |
Safety timer STIM: RANGE 0, RANGE 1 000: 68.2 ms, 5.3 ms 001: 102.2 ms, 10.7 ms 010: 136.3 ms, 16.0 ms 011: 170.4 ms, 21.3 ms 100: 204.5 ms, 26.6 ms 101: 340.8 ms, 32.0 ms 110: 579.3 ms, 37.3 ms 111: 852 ms, 71.5 ms |
D4 | HPFL | R | 0 |
High-power LED failure flag 0: Proper LED operation 1: LED failed (open or shorted) High-power LED failure flag is reset after readout |
D3 | SELSTIM | W | 0 |
Safety timer selection range (write only) 0: Safety timer range 0 1: Safety timer range 1 |
TO | R |
Time-out flag (read only) 0: No time-out event occurred 1: Time-out event occurred. Time-out flag is reset at re-start of the safety timer. |
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D2 | STT | R/W | 0 |
Safety timer trigger 0: LED safety timer is level sensitive 1: LED safety timer is rising edge sensitive This bit is only valid for MODE_CTRL = 10. |
D1 | SFT | R/W | 0 |
Start/Flash timer In write mode, this bit initiates a flash strobe sequence. Notice that this bit is only active when STRB0 input is high. 0: No change in the high-power LED current 1: High-power LED current ramps to the flash current level In read mode, this bit indicates the high-power LED status 0: High-power LEDs are idle 1: Ongoing high-power LED flash strobe |
D0 | Tx-MASK | R/W | 1 |
Flash blanking control bit In write mode, this bit enables/disables the flash blanking/LED current reduction function. 0: Flash blanking disabled 1: LED current is reduced to DC-light level when Tx-MASK input is high In read mode, this flag indicates whether or not the flashlight masking input is activated. Tx-MASK flag is reset after readout of the flag. 0: No flash blanking event occurred 1: Tx-MASK input triggered |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PG | HOTDIE | ILIM | INDC | ||||
R/W-0 | R-0 | R-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
Bit | Field | Type | Reset | Description | |
---|---|---|---|---|---|
D7 | PG | R/W | 0 |
Power good In write mode, this bit selects the functionality of the GPIO/PG output. 0: PG signal is routed to the GPIO port. 1: GPIO PORT VALUE bit is routed to the GPIO port. In read mode, this bit indicates the output voltage conditions. 0: The converter is not operating within the voltage regulation limits. 1: The output voltage is within its nominal value. |
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D6–D5 | HOTDIE | R | 00 |
Instantaneous die temperature 00: TJ < 55°C 01: 55°C < TJ < 70°C 10: TJ > 70°C 11: Thermal shutdown tripped. Indicator flag is reset after readout. |
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D4 | ILIM | R/W | 0 |
Inductor valley current limit The ILIM bit can only be set before the device enters operation (initial shutdown state). Valley current limit: ILIM bit, HC_SEL input, Tx-MASK input 1150 mA: Low, Low, Low 1600 mA: High, Low, Low 30 mA: Low, High, Low 250 mA: High, High, Low 1150 mA: Low, Low, High 1600 mA: High, Low, High —(3): Low, High, High —(3): High, High, High |
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D3–D0 | INDC | R/W | 0000 |
Indicator light control INDC: Privacy indicator INDLED channel 0000: Privacy indicator OFF 0001: INDLED current 2.6 mA(1) 0010: INDLED current 5.2 mA(1) 0011: INDLED current 7.9 mA(1) 0100: Privacy indicator OFF 0101: INDLED current 5.2 mA(1) 0110: INDLED current 10.4 mA(1) 0111: INDLED current 15.8 mA (1) |
INDC: Privacy indicator LEDx channels(2) 1000: 5% PWM dimming ratio 1001: 11% PWM dimming ratio 1010: 17% PWM dimming ratio 1011: 23% PWM dimming ratio 1100: 30% PWM dimming ratio 1101: 36% PWM dimming ratio 1110: 48% PWM dimming ratio 1111: 67% PWM dimming ratio |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SELFCAL | ENPSM | DIR (W) STSTRB1 (R) |
GPIO | GPIOTYPE | ENLED3 | ENLED2 | ENLED1 |
R/W-0 | R/W-1 | R/W-1 | R/W-0 | R/W-1 | R/W-0 | R/W-1 | R/W-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D7 | SELFCAL | W | 0 |
High-current LED forward voltage self-calibration start In write mode, this bit enables/disables the output voltage vs LED forward voltage/current self-calibration procedure. 0: Self-calibration disabled 1: Self-calibration enabled In read mode, this bit returns the status of the self-calibration procedure. 0: Self-calibration ongoing 1: Self-calibration done Notice that this bit is only being reset at the (re-)start of a calibration cycle. |
D6 | ENPSM | R/W | 1 |
Enable or disable power-save mode 0: Power-save mode disabled 1: Power-save mode enabled |
D5 | STSTRB1 | R | 1 |
STRB1 input status (read only) This bit indicates the logic state on the STRB1 state. |
D5 | DIR | W | 1 |
GPIO direction 0: GPIO configured as input 1: GPIO configured as output |
D4 | GPIO | R/W | 0 |
GPIO port value This bit contains the GPIO port value. |
D3 | GPIOTYPE | R/W | 1 |
GPIO port type 0: GPIO is configured as push-pull output 1: GPIO is configured as open-drain output |
D2 | ENLED3 | R/W | 0 |
Enable or Disable High-Current LED3 0: LED3 input is disabled 1: LED3 input is enabled |
D1 | ENLED2 | R/W | 1 |
Enable or disable high-current LED2 0: LED2 input is disabled 1: LED2 input is enabled |
D0 | ENLED1 | R/W | 0 |
Enable or disable high-current LED1 0: LED1 input is disabled 1: LED1 input is enabled |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENTS | LEDHOT | LEDWARN | LEDHDR | OV | |||
R/W-0 | R/W-0 | R-0 | R-0 | R/W-1 | R/W-0 | R/W-0 | R/W-1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D7 | ENTS | R/W | 0 |
Enable or disable LED temperature monitoring 0: LED temperature monitoring disabled 1: LED temperature monitoring enabled |
D6 | LEDHOT | R/W | 0 |
LED excessive temperature flag This bit can be reset by writing a logic level zero. 0: TS input voltage > 0.345 V 1: TS input voltage < 0.345 V |
D5 | LEDWARN | R | 0 |
LED temperature warning flag (read only) This flag is reset after readout. 0: TS input voltage > 1.05 V 1: TS input voltage < 1.05 V |
D4 | LEDHDR | R | 0 |
LED high-current regulator headroom voltage monitoring This bit returns the headroom voltage status of the LED high-current regulators. This value is being updated at the end of a flash strobe, before to the LED current ramp-down phase. 0: Low headroom voltage 1: Sufficient headroom voltage |
D3–D0 | OV | R/W | 1001 |
Output voltage selection In read mode, these bits return the result of the high-current LED forward voltage self-calibration procedure. In write mode, these bits are used to set the target output voltage (see Down Mode In Voltage Regulation Mode). In applications requiring dynamic voltage control, take care to set the new target code after voltage mode operation is enabled (MODE_CTRL = 11 or ENVM bit = 1). OV: Target output voltage 0000: 3.825 V 0001: 3.950 V 0010: 4.075 V 0011: 4.200 V 0100: 4.325 V 0101: 4.450 V 0110: 4.575 V 0111: 4.700 V 1000: 4.825 V 1001: 4.950 V 1010: 5.075 V 1011: 5.200 V 1100: 5.325 V 1101: 5.450 V 1110: 5.575 V 1111: 5.700 V |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVID | |||||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R-1 | R-1 | R-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D2–D0 | REVID | R | 110 |
Silicon Revision ID |