SLVSEE7B June   2018  – January 2021 TPS61372

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout
      2. 7.3.2 Enable and Disable
      3. 7.3.3 Error Amplifier
      4. 7.3.4 Bootstrap Voltage (BST)
      5. 7.3.5 Load Disconnect
      6. 7.3.6 Overvoltage Protection
      7. 7.3.7 Thermal Shutdown
      8. 7.3.8 Start-Up
      9. 7.3.9 Short Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation
      2. 7.4.2 Auto PFM Mode
      3. 7.4.3 Forced PWM Mode
      4. 7.4.4 Mode Selectable
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting the Output Voltage
        3. 8.2.2.3 Selecting the Inductor
        4. 8.2.2.4 Selecting the Output Capacitors
        5. 8.2.2.5 Selecting the Input Capacitors
        6. 8.2.2.6 Loop Stability and Compensation
          1. 8.2.2.6.1 Small Signal Model
        7. 8.2.2.7 Loop Compensation Design Steps
        8. 8.2.2.8 Selecting the Bootstrap Capacitor
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YKB|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Loop Compensation Design Steps

With the small signal models coming out, the next step is to calculate the compensation network parameters with the given inductor and output capacitance.

  1. Set the Crossover Frequency, ƒC.
    • The first step is to set the loop crossover frequency, ƒC. The higher crossover frequency, the faster the loop response is. It is generally accepted that the loop gain cross over no higher than the lower of either 1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency, ƒRHPZ. Then calculate the loop compensation network values of Rc, Cc, and Cp in following sections.
  2. Set the Compensation Resistor, RC.
    • By placing ƒZ below ƒC, for frequencies above ƒC, RC | | REA approximately = RC, so RC × GEA sets the compensation gain. Setting the compensation gain, KCOMP-dB, at ƒZ, results in the total loop gain, T(s) = GPS(s) × HEA(s) × He(s) being zero at ƒC.
    • Therefore, to approximate a single-pole rolloff up to fP2, rearrange Equation 19 to solve for RC so that the compensation gain, KEA, at fC is the negative of the gain, KPS, read at frequency fC for the power stage bode plot or more simply:
      Equation 19. GUID-CE56D9A4-04A6-4B46-A131-EBB6DB2B6AFB-low.gif

      where

      • KEA is gain of the error amplifier network
      • KPS is the gain of the power stage
      • GEA is the transconductance of the amplifier, the typical value of GEA = 175 µA / V
  3. Set the compensation zero capacitor, CC.
    • Place the compensation zero at the power stage pole position of ROUT, COUT to get:
      Equation 20. GUID-85096E82-EA16-4B51-BDE0-0FF75116D1F8-low.gif
    • Set ƒZ = ƒP, and get:
      Equation 21. GUID-DD763818-B5F8-4C16-8526-553ADA1CB92F-low.gif
  4. Set the compensation pole capacitor, CP.
    • Place the compensation pole at the zero produced by the RESR and the COUT. It is useful for canceling unhelpful effects of the ESR zero.
      Equation 22. GUID-7F76CA94-DBE7-4828-97F1-5AA63A1F5AE1-low.gif
      Equation 23. GUID-2325C3AC-2C1F-42C9-B1BC-0D7FE420ACF4-low.gif
    • Set ƒP2 = ƒESR, and get:
      Equation 24. GUID-1A1A24D5-76D1-4660-BC1D-1BFF20D3D742-low.gif
    • If the calculated value of CP is less than 10 pF, it can be neglected.
    Designing the loop for greater than 45° of phase margin and greater than 6-dB gain margin eliminates output voltage ringing during the line and load transient. The RC = 61.9 kΩ , CC = 680 pF for this design example.