SLVSH38 November   2023 TPS61377

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VCC Power Supply
      2. 7.3.2 Enable and Programmable UVLO
      3. 7.3.3 Soft Start
      4. 7.3.4 Switching Frequency
      5. 7.3.5 Programmable Inductor Peak Current Limit
      6. 7.3.6 Shut Down
      7. 7.3.7 Overvoltage Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation
      2. 7.4.2 Forced PWM Mode
      3. 7.4.3 Auto PFM Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting Output Voltage
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Bootstrap Capacitor Selection
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Output Capacitor Selection
        6. 8.2.2.6 Loop Stability
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.6 Loop Stability

The TPS61377 requires external compensation, which allows the loop response to be optimized for each application. The COMP pin is the output of the internal error amplifier. An external compensation network, comprised of resistor RC, and ceramic capacitors CC and CP, is connected to the COMP pin.

The power stage small signal loop response of constant off-time (COT) with peak current control can be modeled by Equation 11.

Equation 11. GUID-EB35EEE0-39C0-4120-B149-8C71205F754C-low.gif

where

  • D is the switching duty cycle.
  • RO is the output load resistance.
  • KCOMP is power stage trans-conductance (inductor peak current / comp voltage), which is 6.5 A/V.
Equation 12. GUID-080645EF-74E2-40B4-A0DF-7A66C1C5F2E9-low.gif

where

  • CO is effective output capacitance.
Equation 13. GUID-C3DDCFC1-E93B-427E-A6E1-85CB39917915-low.gif

where

  • RESR is the equivalent series resistance of the output capacitor.
Equation 14. GUID-78DBE722-9BFB-4FFB-8C6C-866AC7158D57-low.gif

The COMP pin is the output of the internal transconductance amplifier. Equation 15 shows the small signal transfer function of compensation network.

Equation 15. GUID-1911EBD5-1B10-478D-BD16-250EBDE6AD77-low.gif

where

  • GEA is the transconductance of the amplifier, which is 240 uS.
  • REA is the output resistance of the amplifier, which is 100 MΩ.
  • VREF is the reference voltage at the FB pin.
  • VOUT is the output voltage.
  • ƒCOMP1, ƒCOMP2 are the frequency of the poles of the compensation network.
  • ƒCOMZ is the zero's frequency of the compensation network.

The next step is to choose the loop crossover frequency, ƒC. The higher frequency that the loop gain stays above zero before crossing over, the faster the loop response is. It is generally accepted that the loop gain cross over no higher than the lower of either 1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency, ƒRHPZ.

Then set the value of RC, CC, and CP (in Figure 8-1) by following these equations.

Equation 16. GUID-057C8C9F-655B-49DE-803B-31D0E18ECB3D-low.gif

where

  • ƒC is the selected crossover frequency.

The value of CC can be set by Equation 17.

Equation 17. GUID-238E55D2-E0A7-49F1-9444-E9EAC0085923-low.gif

The value of CP can be set by Equation 18.

Equation 18. GUID-407D9CE9-09E8-4E42-82E0-EDA6B2B17CBE-low.gif

If the calculated value of CP is less than 10 pF, it can be left open.

Designing the loop for greater than 45° of phase margin and greater than 10-dB gain margin eliminates output voltage ringing during the line and load transient.