SLVSEL7B April   2019  – October 2019 TPS61390

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Recommended Operating Conditions
    2. 6.2 Absolute Maximum Ratings
    3. 6.3 ESD Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout
      2. 7.3.2 Enable and Disable
      3. 7.3.3 Current Mirror
      4. 7.3.4 Sample and Hold
      5. 7.3.5 High Optical Power Protection
    4. 7.4 Device Functional Mode
      1. 7.4.1 PFM Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirement
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the Rectifier Diode
        2. 8.2.2.2  Selecting the Inductor
        3. 8.2.2.3  Selecting Output Capacitor
        4. 8.2.2.4  Selecting Filter Resistor and Capacitor
        5. 8.2.2.5  Setting the Output Voltage
        6. 8.2.2.6  Selecting Sample Window
        7. 8.2.2.7  Selecting Capacitor for CAP pin
        8. 8.2.2.8  Selecting Capacitor for AVCC pin
        9. 8.2.2.9  Selecting Capacitor for APD pin
        10. 8.2.2.10 Selecting the Resistors of MON1 or MON2
        11. 8.2.2.11 Selecting the Capacitors of MON1 or MON2
        12. 8.2.2.12 Selecting the Resistor of Gain pin
        13. 8.2.2.13 Selecting the Short Current Limit
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over recommended free-air temperature range, VIN = 3.3 V, AVCC = 3.3 V, VMONIN = 20 V to 85 V, TJ = - 40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VIN Input voltage range 2.5 5.5 V
VUVLO Under voltage lock out VIN falling 2.4 2.5 V
Under voltage lock out hysteresis VUVLO rising - VUVLO falling 200 mV
IQ_IN Quiescent current into VIN pin VIN = 3.3 V, VFB =VREF + 0.1 V, No switching, -40 °C ≤ TJ ≤ 85 °C 110 140 uA
IQ_OUT Quiescent current into VOUT pin VIN = 3.3 V, VFB =VREF + 0.1 V,No switching, -40 °C ≤ TJ ≤ 85 °C 340 430 uA
IQ_VCC Quiescent current into AVCC pin AVCC = 3.3 V  -40 °C ≤ TJ ≤ 85 °C 140 180 uA
ISD Shutdown current into VIN pin 2.5 V ≤ VIN ≤ 5.5 V, EN = 0, -40 °C ≤ TJ ≤ 85 °C 1 uA
Shutdown current into VOUT pin  EN = 0, -40 °C ≤ TJ ≤ 85 °C 1 uA
Shutdown current into AVCC pin AVCC = 3.3 V, EN = 0, -40 °C ≤ TJ ≤ 85 °C 1 uA
OUTPUT
VOUT Output voltage range 85 V
VREF Feedback regulation reference voltage VIN = 2.5 V to 5.5 V, TJ = 25 °C 1.188 1.2 1.212 V
VIN = 2.5 V to 5.5 V, -40 °C ≤ TJ ≤ 125 °C 1.182 1.2 1.218 V
IFB Feedback input leakage current 1 25 nA
POWER SWITCH
RDS(on) Low-side FET on resistance 3 V ≤ VIN ≤ 5.5 V 900 1300 mΩ
SWITCHING CHARACTERISTIC
fSW Switching frequency VIN = 3.3 V, VOUT = 60 V 600 700 800 kHz
CURRENT MIRROR
kMON1 4:5 Current mirror gain IAPD = 5 µA to 200 µA 0.76 0.8 0.84
kMON2 1:5 Current mirror gain IAPD = 100 µA to 2 mA 0.19 0.2 0.21
VMON MON1 / MON2 Threshold 380 400 420 mV
VAPD_DRP Current mirror voltage drop IAPD = 1 mA 2.2 2.5 2.8 V
IAPD = 5 µA 2.45 V
IBIAS Current mirror bias current 15 20 25 µA
SAMPLE / HOLD
VERROR Sample/hold output error steady,+/-6 sigma IAPD = 20 uA, GAIN = 0.8, RMON = 3 kΩ -15 +15 %
VERROR Sample/hold output error steady,+/-6 sigma IAPD = 500 µA, GAIN = 0.2, RMON = 3 kΩ -5 +5 %
tSP_DEL Amplifier settling down time 10 µs
tGAIN_COMP Gain selection comparator time +/-20% gap of threshold 8 µs
VDROP_SP Drop voltage during sample/hold Sample voltage sensing value variation at 10-100 µs, (Max-Min)/Average 1 %
CURRENT LIMIT
ILIM_SW Peak switching current limit VIN = 3.3 V, VOUT = 60 V 800 1000 1200 mA
ISHORT High optical power current limit RISHORT = 25 kΩ 3.7 4 4.3 mA
RISHORT = 50 kΩ 1.8 2 2.2 mA
CONTROL (EN, SAMPLE, GAIN)
VEN_H EN Logic high threshold 1.2 V
VEN_L EN Logic low threshold 0.4 V
REN EN pull down resistor 800 kΩ
VSAMPLE_H Sample Logic high threshold 0.7 x AVCC V
VSAMPLE_L Sample Logic low threshold 0.3 x AVCC V
VGAIN_H Gain Logic high threshold 0.7 x AVCC V
VGAIN_L Gain Logic low threshold 0.3 x AVCC V
RGAIN_OUT Output resistor 5.5 kΩ
TIMING
tSS Soft start time Ref voltage 0 to 1.2V 4.8 ms
tDELAY Delay time for high optical power protection IAPD = 5 mA, ISHORT = 3 mA 0.5 µs
THERMAL PROTECTION
TSD Thermal shutdown threshold TJ rising 150 °C
TSD_HYS Thermal shutdown hysteresis TJ falling below TSD 20 °C