SLVSEL7B April   2019  – October 2019 TPS61390

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Recommended Operating Conditions
    2. 6.2 Absolute Maximum Ratings
    3. 6.3 ESD Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout
      2. 7.3.2 Enable and Disable
      3. 7.3.3 Current Mirror
      4. 7.3.4 Sample and Hold
      5. 7.3.5 High Optical Power Protection
    4. 7.4 Device Functional Mode
      1. 7.4.1 PFM Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirement
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the Rectifier Diode
        2. 8.2.2.2  Selecting the Inductor
        3. 8.2.2.3  Selecting Output Capacitor
        4. 8.2.2.4  Selecting Filter Resistor and Capacitor
        5. 8.2.2.5  Setting the Output Voltage
        6. 8.2.2.6  Selecting Sample Window
        7. 8.2.2.7  Selecting Capacitor for CAP pin
        8. 8.2.2.8  Selecting Capacitor for AVCC pin
        9. 8.2.2.9  Selecting Capacitor for APD pin
        10. 8.2.2.10 Selecting the Resistors of MON1 or MON2
        11. 8.2.2.11 Selecting the Capacitors of MON1 or MON2
        12. 8.2.2.12 Selecting the Resistor of Gain pin
        13. 8.2.2.13 Selecting the Short Current Limit
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

The basic PCB board layout requires a separation of sensitive signal and power paths. If the layout is not carefully done, the regulator could suffer from the instability or noise problems. Use the following checklist to get good performance for a well-designed board:

  • Minimize the high current path including the switch FET, rectifier FET, and the output capacitor. This loop contains high di / dt switching currents (nano seconds per ampere) and easy to transduce the high frequency noise;
  • Place the noise sensitive network like sample hold and current mirror output (MON1, MON2) being far away from the SW trace;
  • Split the ground for the power GND, signal GND. Use a separate ground trace to connect the sample/hold and boost circuitry. Connect this ground trace to the main power ground at a single point to minimize circulating currents.