SLVSEL7B April   2019  – October 2019 TPS61390

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Recommended Operating Conditions
    2. 6.2 Absolute Maximum Ratings
    3. 6.3 ESD Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout
      2. 7.3.2 Enable and Disable
      3. 7.3.3 Current Mirror
      4. 7.3.4 Sample and Hold
      5. 7.3.5 High Optical Power Protection
    4. 7.4 Device Functional Mode
      1. 7.4.1 PFM Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirement
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the Rectifier Diode
        2. 8.2.2.2  Selecting the Inductor
        3. 8.2.2.3  Selecting Output Capacitor
        4. 8.2.2.4  Selecting Filter Resistor and Capacitor
        5. 8.2.2.5  Setting the Output Voltage
        6. 8.2.2.6  Selecting Sample Window
        7. 8.2.2.7  Selecting Capacitor for CAP pin
        8. 8.2.2.8  Selecting Capacitor for AVCC pin
        9. 8.2.2.9  Selecting Capacitor for APD pin
        10. 8.2.2.10 Selecting the Resistors of MON1 or MON2
        11. 8.2.2.11 Selecting the Capacitors of MON1 or MON2
        12. 8.2.2.12 Selecting the Resistor of Gain pin
        13. 8.2.2.13 Selecting the Short Current Limit
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RTE Package
16-Pin WQFN
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
VSP 1 O Sample/Hold voltage output with single-ended output.
GAIN 2 I GAIN of the current mirror selection indicator of the sample/hold output:
Output low: sample/hold for current mirror gain 4 : 5;
Output high: sample/hold for current mirror gain 1 : 5;
This pin can also be any input pin:
Input low: sample/hold for current mirror gain 4 : 5;
Input high: sample/hold for current mirror gain 1 : 5
MON2 3 O Current mirror output pin of 1 : 5 ratio (Mirror current: APD current)
MON1 4 O Current mirror output pin of 4 : 5 ratio (Mirror current: APD current)
APD 5 O Power supply for the APD, connect this pin with the cathode of APD
MONIN 6 I Current mirror input pin
GND 7 – Power Ground
SW 8 PWR The switching node pin of the converter. It is connected to the drain of the internal low-side power MOSFET and the source of the internal high-side power MOSFET
CAP 9 O Connecting a capacitor externally to lower the noise for current mirror.
VIN 10 I IC power supply input
ISHORT 11 O Programming the current limit for high optical power protection by a resistor between this pin and GND.
FB 12 I Feedback voltage
EN 13 I Enable logic input. Logic high level enables the device. Logic low level disables the device and turns it into shutdown mode
SAMPLE 14 I The sample trigger pin, the rising edge of this pin to trigger the sample and falling edge to hold the sampled voltage.
AVCC 15 I Power supply for the sample/hold circuitry
AGND 16 – Analog ground for the sample / hold and current mirror circuitry
Exposed Thermal Pad Connect with GND, TI recommends connecting to Power GND on PCB