Refer to the PDF data sheet for device specific package drawings
The TPS6200x devices are a family of low-noise synchronous step-down DC/DC converters that are ideally suited for systems powered from a 1-cell Li-ion battery or from a 2- to 3-cell NiCd, NiMH, or alkaline battery. The TPS6200x operates typically down to an input voltage of 1.8 V, with a specified minimum input voltage of 2 V.
The TPS62000 operates over a free-air temperature range of –40°C to 85°C.The device is available in the 10-pin (DGS) microsmall outline package (VSSOP).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS6200x | VSSOP (10) | 3.00 mm × 3.00 mm |
Changes from E Revision (August 2008) to F Revision
VOLTAGE OPTIONS | PACKAGE(1) | MARKING |
---|---|---|
VSSOP | DGS | |
Adjustable | TPS62000DGS | AIH |
0.9 V | TPS62001DGS | AII |
1 V | TPS62002DGS | AIJ |
1.2 V | TPS62003DGS | AIK |
1.5 V | TPS62004DGS | AIL |
1.8 V | TPS62005DGS | AIM |
1.9 V | TPS62008DGS | AJI |
2.5 V | TPS62006DGS | AIN |
3.3 V | TPS62007DGS | AIO |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN | 8 | I | Enable. A logic high enables the converter, logic low forces the device into shutdown mode reducing the supply current to less than 1 μA. |
FB | 5 | I | Feedback pin for the fixed output voltage option. For the adjustable version an external resistive divider is connected to FB. The internal voltage divider is disabled for the adjustable version. |
FC | 2 | — | Supply bypass pin. A 0.1-μF coupling capacitor should be connected as close as possible to this pin for good high frequency input voltage supply filtering. |
GND | 3 | — | Ground |
ILIM | 6 | I | Switch current limit. Connect ILIM to GND to set the switch current limit to typically 600 mA, or connect this pin to VIN to set the current limit to typically 1200 mA. |
L | 9 | I/O | Connect the inductor to this pin. L is the switch pin connected to the drain of the internal power MOSFETS. |
PG | 4 | O | Power good comparator output. This is an open-drain output. A pull-up resistor should be connected between PG and VOUT. The output goes active high when the output voltage is greater than 92% of the nominal value. |
PGND | 10 | — | Power ground. Connect all power grounds to PGND. |
SYNC | 7 | I | Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an external clock signal with CMOS level: SYNC = High: Low-noise mode enabled, fixed frequency PWM operation is forced SYNC = Low (GND): Power save mode enabled, PFM/PWM mode enabled |
VIN | 1 | I | Supply voltage input |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltages on pin VIN and FC(2) | –0.3 | 6 | V | |
Voltages on pins EN, ILIM, SYNC, PG, FB, L(2) | –0.3 | VIN + 0.3 | V | |
Peak switch current | 1.6 | A | ||
TJ | Operating junction temperature | –40 | 150 | °C |
Lead temperature (soldering, 10 sec) | 260 | °C | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN | Supply voltage | 2 | 5.5 | V | |
VOUT | Output voltage range for adjustable output voltage version | 0.8 | VIN | V | |
IOUT | Output current for 3-cell operation (VIN ≥ 2.5 V; L = 10 μH, f = 750 kHz) | 600 | mA | ||
IOUT | Output current for 2-cell operation (VIN ≥ 2 V; L = 10 μH, f = 750 kHz) | 200 | mA | ||
L | Inductor(1) (see Note 2) | 10 | μH | ||
CIN | Input capacitor(1) | 10 | μF | ||
COUT | Output capacitor(1) (VOUT ≥ 1.8 V) | 10 | μF | ||
COUT | Output capacitor(1) VOUT < 1.8 V) | 47 | μF | ||
TA | Operating ambient temperature | –40 | 85 | °C | |
TJ | Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS6200x | UNIT | |
---|---|---|---|
DGS [VSSOP] | |||
10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 160 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 51 | °C/W |
RθJB | Junction-to-board thermal resistance | 73 | °C/W |
ψJT | Junction-to-top characterization parameter | 5.0 | °C/W |
ψJB | Junction-to-board characterization parameter | 72 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SUPPLY CURRENT | |||||||
VIN | Input voltage range | IOUT = 0 mA to 600 mA | 2.5 | 5.5 | V | ||
IOUT = 0 mA to 200 mA | 2 | 5.5 | |||||
I(Q) | Operating quiescent current | IOUT = 0 mA, SYNC = GND (PFM-mode enabled) | 50 | 75 | μA | ||
I(SD) | Shutdown current | EN = GND | 0.1 | 1 | μA | ||
ENABLE | |||||||
VIH | EN high-level input voltage | 1.3 | V | ||||
VIL | EN low-level input voltage | 0.4 | V | ||||
Ilkg | EN input leakage current | EN = GND or VIN | 0.01 | 0.1 | μA | ||
V(UVLO) | Undervoltage lockout threshold | 1.2 | 1.6 | 1.95 | V | ||
POWER SWITCH AND CURRENT LIMIT | |||||||
RDS(on) | P-channel MOSFET on-resistance | VIN = VGS = 3.6 V, I = 200 mA | 200 | 280 | 410 | mΩ | |
VIN = VGS = 2 V, I = 200 mA | 480 | ||||||
P-channel leakage current | VDS = 5.5 V | 1 | μA | ||||
N-channel MOSFET on-resistance | VIN = VGS = 3.6 V, IOUT = 200 mA | 200 | 280 | 410 | mΩ | ||
VIN = VGS = 2 V, IOUT = 200 mA | 500 | ||||||
N-channel leakage current | VDS = 5.5 V | 1 | μA | ||||
I(LIM) | P-channel current limit | 2.5 V ≤ VIN ≤ 5.5 V, ILIM = VIN | 800 | 1200 | 1600 | mA | |
2 V ≤ VIN ≤ 5.5 V, ILIM = GND | 390 | 600 | 900 | ||||
VIH | ILIM high-level input voltage | 1.3 | V | ||||
VIL | ILIM low-level input voltage | 0.4 | V | ||||
Ilkg | ILIM input leakage current | ILIM = GND or VIN | 0.01 | 0.1 | μA | ||
POWER GOOD OUTPUT (see (1)) | |||||||
V(PG) | Power good threshold | Feedback voltage falling | 88% VOUT | 92% VOUT | 94% VOUT | V | |
Power good hysteresis | 2.5% VOUT | V | |||||
VOL | PG output low voltage | V(FB) = 0.8 × VOUT nominal, I(sink) = 10 μA | 0.3 | V | |||
Ilkg | PG output leakage current | V(FB) = VOUT nominal | 0.01 | 1 | μA | ||
Minimum supply voltage for valid power good signal | 1.2 | V | |||||
OSCILLATOR | |||||||
fs | Oscillator frequency | 500 | 750 | 1000 | kHz | ||
f(SYNC) | Synchronization range | CMOS-logic clock signal on SYNC pin | 500 | 1000 | kHz | ||
VIH | SYNC high level input voltage | 1.3 | V | ||||
VIL | SYNC low level input voltage | 0.4 | V | ||||
Ilkg | SYNC input leakage current | SYNC = GND or VIN | 0.01 | 0.1 | μA | ||
Duty cycle of external clock signal | 20% | 60% | |||||
VO | Adjustable output voltage range | TPS62000 | 0.8 | 5.5 | V | ||
Vref | Reference voltage | TPS6200x | 0.45 | V | |||
VOUT | Fixed output voltage | TPS62000 adjustable | VIN = 2.5 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | V | |
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
TPS62001 0.9 V | VIN = 2.5 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | ||||
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
TPS62002 1 V |
VIN = 2.5 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | ||||
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
TPS62003 1.2 V |
VIN = 2.5 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | ||||
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
TPS62004 1.5 V |
VIN = 2.5 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | ||||
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
TPS62005 1.8 V |
VIN = 2.5 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | ||||
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
TPS62008 1.9 V |
VIN = 2.5 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | ||||
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
TPS62006 2.5 V |
VIN = 2.7 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | ||||
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
TPS62007 3.3 V |
VIN = 3.6 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | ||||
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
Line regulation | VIN = VOUT + 0.5 V (min. 2 V) to 5.5 V, IOUT = 10 mA | 0.05 | %/V | ||||
Load regulation | VIN = 5.5 V; IOUT = 10 mA to 600 mA | 0.6% | |||||
η | Efficiency | VIN = 5 V; VOUT = 3.3 V; IOUT = 300 mA | 95% | ||||
VIN = 3.6 V; VOUT = 2.5 V; IOUT = 200 mA | |||||||
Start-up time | IOUT = 0 mA, time from active EN to VOUT | 0.4 | 2 | ms |
The TPS6200x is a step down converter operating in a current mode PFM/PWM scheme with a typical switching frequency of 750 kHz.
At moderate to heavy loads, the converter operates in the pulse width modulation (PWM) and at light loads the converter enters a power save mode (pulse frequency modulation, PFM) to keep the efficiency high.
In the PWM mode operation, the part operates at a fixed frequency of 750 kHz. At the beginning of each clock cycle, the high side P-channel MOSFET is turned on. The current in the inductor ramps up and is sensed via an internal circuit. The high side switch is turned off when the sensed current causes the PFM/PWM comparator to trip when the output voltage is in regulation or when the inductor current reaches the current limit (set by ILIM). After a minimum dead time preventing shoot through current, the low side N-channel MOSFET is turned on and the current ramps down again. As the clock cycle is completed, the low side switch is turned off and the next clock cycle starts.
In discontinuous conduction mode (DCM), the inductor current ramps to zero before the end of each clock cycle. In order to increase the efficiency the load comparator turns off the low side MOSFET before the inductor current becomes negative. This prevents reverse current flowing from the output capacitor through the inductor and low side MOSFET to ground that would cause additional losses.
As the load current decreases and the peak inductor current does not reach the power save mode threshold of typically 120 mA for more than 15 clock cycles, the converter enters a pulse frequency modulation (PFM) mode.
In the PFM mode, the converter operates with:
Thus maintaining the highest efficiency at light load currents. In this mode, the output voltage is monitored with the error amplifier. As soon as the output voltage falls below the nominal value, the high side switch is turned on and the inductor current ramps up. When the inductor current reaches the peak current of typical: 150 mA + 50 mA/V × (VIN – VOUT), the high side switch turns off and the low side switch turns on. As the inductor current ramps down, the low side switch is turned off before the inductor current becomes negative which completes the cycle. When the output voltage falls below the nominal voltage again, the next cycle is started.
The converter enters the PWM mode again as soon as the output voltage can not be maintained with the typical peak inductor current in the PFM mode.
The control loop is internally compensated reducing the amount of external components.
The switch current is internally sensed and the maximum current limit can be set to typical 600 mA by connecting ILIM to ground; or, to typically 1.2 A by connecting ILIM to VIN.
An antiringing switch is implemented in order to reduce the EMI radiated from the converter during discontinuous conduction mode (DCM). In DCM, the inductor current ramps to zero before the end of each switching period. The internal load comparator turns off the low side switch at that instant thus preventing the current flowing backward through the inductance which increases the efficiency. An antiringing switch across the inductor prevents parasitic oscillation caused by the residual energy stored in the inductance (see Figure 11).
NOTE
The antiringing switch is only activated in the fixed output voltage versions. It is not enabled for the adjustable output voltage version TPS62000.
Logic low on EN forces the TPS6200x into shutdown. In shutdown, the power switch, drivers, voltage reference, oscillator, and all other functions are turned off. The supply current is reduced to less than 1 μA in the shutdown mode.
An undervoltage lockout circuit provides the save operation of the device. It prevents the converter from turning on when the voltage on VIN is less than typically 1.6 V.
The power good (PG) comparator has an open drain output capable of sinking typically 10 μA. The PG is only active when the device is enabled (EN = high). When the device is disabled (EN = low), the PG pin is high impedance.
The PG output is only valid after a 100 μs delay after the device is enabled and the supply voltage is greater than 1.2 V. This is only important in cases where the pullup resistor of the PG pin is connected to an external voltage source which might cause an initial spike (false high signal) within the first 100 μs after the input voltage exceeds 1.2 V. This initial spike can be filtered with a small R-C filter to avoid false power good signals during start-up.
If the PG pin is connected to the output of the TPS62000 with a pullup resistor, no initial spike (false high signal) occurs and no precautions have to be taken during start-up.
The PG pin becomes active high when the output voltage exceeds typically 94.5% of its nominal value. Leave the PG pin unconnected when not used.
The TPS6200x is a synchronous current-mode PWM converter with integrated – and P-channel power MOSFET switches. Synchronous rectification is used to increase efficiency and to reduce external component count. To achieve the highest efficiency over a wide load current range, the converter enters a power-saving pulse-frequency modulation (PFM) mode at light load currents. Operating frequency is typically 750 kHz, allowing the use of small inductor and capacitor values. The device can be synchronized to an external clock signal in the range of 500 kHz to 1 MHz. For low-noise operation, the converter can be operated in the PWM mode and the internal antiringing switch reduces noise and EMI. In the shutdown mode, the current consumption is reduced to less than 1 μA. The TPS62000 is available in the 10-pin (DGS) microsmall outline package (VSSOP). The device operates over a free-air temperature range of –40°C to 85°C.
As the enable pin (EN) goes high, the soft-start function generates an internal voltage ramp. This causes the start-up current to slowly rise preventing output voltage overshoot and high inrush currents. The soft-start duration is typical 1 ms (see Figure 12). When the soft-start function is completed, the error amplifier is connected directly to the internal voltage reference.
If no clock signal is applied, the converter operates with a typical switching frequency of 750 kHz. It is possible to synchronize the converter to an external clock within a frequency range from 500 kHz to 1000 kHz. The device automatically detects the rising edge of the first clock and is synchronized immediately to the external clock. If the clock signal is stopped, the converter automatically switches back to the internal clock and continues operation without interruption. The switch over is initiated if no rising edge on the SYNC pin is detected for a duration of four clock cycles. Therefore, the maximum delay time can be 8 μs in case the internal clock has a minimum frequency of 500 kHz.
In case the device is synchronized to an external clock, the power save mode is disabled and the device stays in forced PWM mode.
Connecting the SYNC pin to the GND pin enables the power save mode. The converter operates in the PWM mode at moderate to heavy loads and in the PFM mode during light loads maintaining high efficiency over a wide load current range.
Connecting the SYNC pin to the VIN pin forces the converter to operate permanently in the PWM mode even at light or no load currents. The advantage is the converter operates with a fixed switching frequency that allows simple filtering of the switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power save mode during light loads (see ).
It is possible to switch from forced PWM mode to the power save mode during operation.
The flexible configuration of the SYNC pin during operation of the device allows efficient power management by adjusting the operation of the TPS6200x to the specific system requirements.
As the input voltage approaches the output voltage and the duty cycle exceeds typical 95%, the converter turns the P-channel high side switch continuously on. In this mode, the output voltage is equal to the input voltage minus the voltage drop across the P-channel MOSFET.
In case the converter operates in the forced PWM mode and there is no load connected to the output, the converter will regulate the output voltage by allowing the inductor current to reverse for a short period of time.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS6200x device family are highly efficient synchronous step down DC/DC converters providing adjustable output voltages from 0.9 V to VIN and fixed output voltages.
When the adjustable output voltage version (TPS62000DGS) is used, the output voltage is set by the external resistor divider (see Figure 5).
The output voltage is calculated as:
with R1 + R2 ≤ 1 MΩ
R1 + R2 should not be greater than 1 MW because of stability reasons.
For stability reasons, a small bypass capacitor (C(ff)) is required in parallel to the upper feedback resistor, refer to Figure 5. The bypass capacitor value can be calculated as:
R1 is the upper resistor of the voltage divider. For C(ff), choose a value which comes closest to the computed result.
A 10 μH minimum output inductor is used with the TPS6200x. Values larger than 22 μH or smaller than 10 μH may cause stability problems because of the internal compensation of the regulator.
For output voltages greater than 1.8 V, a 22 μH inductance might be used in order to improve the efficiency of the converter.
After choosing the inductor value of typically 10 μH, two additional inductor parameters should be considered: first the current rating of the inductor and second the DC resistance.
The DC resistance of the inductance influences directly the efficiency of the converter. Therefore, an inductor with lowest DC resistance should be selected for highest efficiency.
In order to avoid saturation of the inductor, the inductor should be rated at least for the maximum output current plus the inductor ripple current which is calculated as:
where
The highest inductor current occurs at maximum VIN.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the TPS6200x which is 1.6 A with ILIM = VIN and 900 mA with ILIM = GND. See Table 1 for recommended inductors.
OUTPUT CURRENT | INDUCTOR VALUE | COMPONENT SUPPLIER | COMMENTS |
---|---|---|---|
0 mA to 600 mA | 10 μH | Coilcraft DO3316P-103 Coilcraft DT3316P-103 Sumida CDR63B-100 Sumida CDRH5D28-100 |
High efficiency |
Coilcraft DO1608C-103 Sumida CDRH4D28-100 |
Smallest solution | ||
0 mA to 300 mA | 10 μH | Coilcraft DO1608C-103 | High efficiency |
Murata LQH4C100K04 | Smallest solution |
For best performance, a low ESR output capacitor is needed. At output voltages greater than 1.8 V, ceramic output capacitors can be used to show the best performance. Output voltages below 1.8 V require a larger output capacitor and ESR value to improve the performance and stability of the converter.
OUTPUT VOLTAGE RANGE | OUTPUT CAPACITOR | OUTPUT CAPACITOR ESR |
---|---|---|
1.8 V ≤ VIN ≤ 5.5 V | Co ≥ 10 μF | ESR ≤ 120 mΩ |
0.8 V ≤ VIN < 1.8 V | Co ≥ 47 μF | ESR > 50 mΩ |
See Table 3 for recommended capacitors.
If an output capacitor is selected with an ESR value ≤ 120 mΩ, its RMS ripple current rating always meets the application requirements. Just for completeness, the RMS ripple current is calculated as:
The overall output ripple voltage is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor:
Where the highest output voltage ripple occurs at the highest input voltage VI.
CAPACITOR VALUE | ESR/mΩ | COMPONENT SUPPLIER | COMMENTS |
---|---|---|---|
10 μF | 50 | Taiyo Yuden JMK316BJ106KL | Ceramic |
47 μF | 100 | Sanyo 6TPA47M | POSCAP |
68 μF | 100 | Spraque 594D686X0010C2T | Tantalum |
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes.
The input capacitor should have a minimum value of 10 μF and can be increased without any limit for better input voltage filtering.
The input capacitor should be rated for the maximum input ripple current calculated as:
The worst case RMS ripple current occurs at D = 0.5 and is calculated as:
Ceramic capacitor show a good performance because of their low ESR value, and they are less sensitive against voltage transients compared to tantalum capacitors.
Place the input capacitor as close as possible to the input pin of the IC for best performance.
NOTE:
For low noise operation connect SYNC to VIN