Refer to the PDF data sheet for device specific package drawings
The TPS6200x devices are a family of low-noise synchronous step-down DC/DC converters that are ideally suited for systems powered from a 1-cell Li-ion battery or from a 2- to 3-cell NiCd, NiMH, or alkaline battery. The TPS6200x operates typically down to an input voltage of 1.8 V, with a specified minimum input voltage of 2 V.
The TPS62000 operates over a free-air temperature range of –40°C to 85°C.The device is available in the 10-pin (DGS) microsmall outline package (VSSOP).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS6200x | VSSOP (10) | 3.00 mm × 3.00 mm |
Changes from E Revision (August 2008) to F Revision
VOLTAGE OPTIONS | PACKAGE(1) | MARKING |
---|---|---|
VSSOP | DGS | |
Adjustable | TPS62000DGS | AIH |
0.9 V | TPS62001DGS | AII |
1 V | TPS62002DGS | AIJ |
1.2 V | TPS62003DGS | AIK |
1.5 V | TPS62004DGS | AIL |
1.8 V | TPS62005DGS | AIM |
1.9 V | TPS62008DGS | AJI |
2.5 V | TPS62006DGS | AIN |
3.3 V | TPS62007DGS | AIO |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN | 8 | I | Enable. A logic high enables the converter, logic low forces the device into shutdown mode reducing the supply current to less than 1 μA. |
FB | 5 | I | Feedback pin for the fixed output voltage option. For the adjustable version an external resistive divider is connected to FB. The internal voltage divider is disabled for the adjustable version. |
FC | 2 | — | Supply bypass pin. A 0.1-μF coupling capacitor should be connected as close as possible to this pin for good high frequency input voltage supply filtering. |
GND | 3 | — | Ground |
ILIM | 6 | I | Switch current limit. Connect ILIM to GND to set the switch current limit to typically 600 mA, or connect this pin to VIN to set the current limit to typically 1200 mA. |
L | 9 | I/O | Connect the inductor to this pin. L is the switch pin connected to the drain of the internal power MOSFETS. |
PG | 4 | O | Power good comparator output. This is an open-drain output. A pull-up resistor should be connected between PG and VOUT. The output goes active high when the output voltage is greater than 92% of the nominal value. |
PGND | 10 | — | Power ground. Connect all power grounds to PGND. |
SYNC | 7 | I | Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an external clock signal with CMOS level: SYNC = High: Low-noise mode enabled, fixed frequency PWM operation is forced SYNC = Low (GND): Power save mode enabled, PFM/PWM mode enabled |
VIN | 1 | I | Supply voltage input |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltages on pin VIN and FC(2) | –0.3 | 6 | V | |
Voltages on pins EN, ILIM, SYNC, PG, FB, L(2) | –0.3 | VIN + 0.3 | V | |
Peak switch current | 1.6 | A | ||
TJ | Operating junction temperature | –40 | 150 | °C |
Lead temperature (soldering, 10 sec) | 260 | °C | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN | Supply voltage | 2 | 5.5 | V | |
VOUT | Output voltage range for adjustable output voltage version | 0.8 | VIN | V | |
IOUT | Output current for 3-cell operation (VIN ≥ 2.5 V; L = 10 μH, f = 750 kHz) | 600 | mA | ||
IOUT | Output current for 2-cell operation (VIN ≥ 2 V; L = 10 μH, f = 750 kHz) | 200 | mA | ||
L | Inductor(1) (see Note 2) | 10 | μH | ||
CIN | Input capacitor(1) | 10 | μF | ||
COUT | Output capacitor(1) (VOUT ≥ 1.8 V) | 10 | μF | ||
COUT | Output capacitor(1) VOUT < 1.8 V) | 47 | μF | ||
TA | Operating ambient temperature | –40 | 85 | °C | |
TJ | Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS6200x | UNIT | |
---|---|---|---|
DGS [VSSOP] | |||
10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 160 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 51 | °C/W |
RθJB | Junction-to-board thermal resistance | 73 | °C/W |
ψJT | Junction-to-top characterization parameter | 5.0 | °C/W |
ψJB | Junction-to-board characterization parameter | 72 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SUPPLY CURRENT | |||||||
VIN | Input voltage range | IOUT = 0 mA to 600 mA | 2.5 | 5.5 | V | ||
IOUT = 0 mA to 200 mA | 2 | 5.5 | |||||
I(Q) | Operating quiescent current | IOUT = 0 mA, SYNC = GND (PFM-mode enabled) | 50 | 75 | μA | ||
I(SD) | Shutdown current | EN = GND | 0.1 | 1 | μA | ||
ENABLE | |||||||
VIH | EN high-level input voltage | 1.3 | V | ||||
VIL | EN low-level input voltage | 0.4 | V | ||||
Ilkg | EN input leakage current | EN = GND or VIN | 0.01 | 0.1 | μA | ||
V(UVLO) | Undervoltage lockout threshold | 1.2 | 1.6 | 1.95 | V | ||
POWER SWITCH AND CURRENT LIMIT | |||||||
RDS(on) | P-channel MOSFET on-resistance | VIN = VGS = 3.6 V, I = 200 mA | 200 | 280 | 410 | mΩ | |
VIN = VGS = 2 V, I = 200 mA | 480 | ||||||
P-channel leakage current | VDS = 5.5 V | 1 | μA | ||||
N-channel MOSFET on-resistance | VIN = VGS = 3.6 V, IOUT = 200 mA | 200 | 280 | 410 | mΩ | ||
VIN = VGS = 2 V, IOUT = 200 mA | 500 | ||||||
N-channel leakage current | VDS = 5.5 V | 1 | μA | ||||
I(LIM) | P-channel current limit | 2.5 V ≤ VIN ≤ 5.5 V, ILIM = VIN | 800 | 1200 | 1600 | mA | |
2 V ≤ VIN ≤ 5.5 V, ILIM = GND | 390 | 600 | 900 | ||||
VIH | ILIM high-level input voltage | 1.3 | V | ||||
VIL | ILIM low-level input voltage | 0.4 | V | ||||
Ilkg | ILIM input leakage current | ILIM = GND or VIN | 0.01 | 0.1 | μA | ||
POWER GOOD OUTPUT (see (1)) | |||||||
V(PG) | Power good threshold | Feedback voltage falling | 88% VOUT | 92% VOUT | 94% VOUT | V | |
Power good hysteresis | 2.5% VOUT | V | |||||
VOL | PG output low voltage | V(FB) = 0.8 × VOUT nominal, I(sink) = 10 μA | 0.3 | V | |||
Ilkg | PG output leakage current | V(FB) = VOUT nominal | 0.01 | 1 | μA | ||
Minimum supply voltage for valid power good signal | 1.2 | V | |||||
OSCILLATOR | |||||||
fs | Oscillator frequency | 500 | 750 | 1000 | kHz | ||
f(SYNC) | Synchronization range | CMOS-logic clock signal on SYNC pin | 500 | 1000 | kHz | ||
VIH | SYNC high level input voltage | 1.3 | V | ||||
VIL | SYNC low level input voltage | 0.4 | V | ||||
Ilkg | SYNC input leakage current | SYNC = GND or VIN | 0.01 | 0.1 | μA | ||
Duty cycle of external clock signal | 20% | 60% | |||||
VO | Adjustable output voltage range | TPS62000 | 0.8 | 5.5 | V | ||
Vref | Reference voltage | TPS6200x | 0.45 | V | |||
VOUT | Fixed output voltage | TPS62000 adjustable | VIN = 2.5 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | V | |
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
TPS62001 0.9 V | VIN = 2.5 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | ||||
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
TPS62002 1 V |
VIN = 2.5 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | ||||
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
TPS62003 1.2 V |
VIN = 2.5 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | ||||
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
TPS62004 1.5 V |
VIN = 2.5 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | ||||
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
TPS62005 1.8 V |
VIN = 2.5 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | ||||
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
TPS62008 1.9 V |
VIN = 2.5 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | ||||
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
TPS62006 2.5 V |
VIN = 2.7 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | ||||
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
TPS62007 3.3 V |
VIN = 3.6 V to 5.5 V; 0 mA ≤ IOUT ≤ 600 mA | –3% | 4% | ||||
10 mA < IOUT ≤ 600 mA | –3% | 3% | |||||
Line regulation | VIN = VOUT + 0.5 V (min. 2 V) to 5.5 V, IOUT = 10 mA | 0.05 | %/V | ||||
Load regulation | VIN = 5.5 V; IOUT = 10 mA to 600 mA | 0.6% | |||||
η | Efficiency | VIN = 5 V; VOUT = 3.3 V; IOUT = 300 mA | 95% | ||||
VIN = 3.6 V; VOUT = 2.5 V; IOUT = 200 mA | |||||||
Start-up time | IOUT = 0 mA, time from active EN to VOUT | 0.4 | 2 | ms |