SLVSC55C August   2013  – November 2021 TPS62090-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Disable (EN)
      2. 7.3.2  Soft Start (SS) and Hiccup Current Limit During Start-Up
      3. 7.3.3  Voltage Tracking (SS)
      4. 7.3.4  Short-Circuit Protection (Hiccup Mode)
      5. 7.3.5  Output Discharge Function
      6. 7.3.6  Power Good Output (PG)
      7. 7.3.7  Frequency Set Pin (FREQ)
      8. 7.3.8  Undervoltage Lockout (UVLO)
      9. 7.3.9  Thermal Shutdown
      10. 7.3.10 Charge Pump (CP, CN)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse Width Modulation Operation
      2. 7.4.2 Power Save Mode Operation
      3. 7.4.3 Low-Dropout Operation (100% Duty Cycle)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Input and Output Capacitor Selection
        3. 8.2.2.3 Setting the Output Voltage
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.2 Power Save Mode Operation

As the load current decreases, the converter enters power save mode operation. During power save mode, the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current while maintaining high efficiency. The power save mode is based on a fixed on-time architecture following Equation 3. When operating at 1.4 MHz, the on-time is twice as long as the on-time for 2.8-MHz operation, resulting in larger output voltage ripple, as shown in Figure 8-11 and Figure 8-12, and slightly higher output voltage at no load, as shown in Figure 8-8 and Figure 8-9. To have the same output voltage ripple at 1.4 MHz during PFM mode, either the output capacitor or the inductor value must be increased. As an example, operating at 2.8 MHz using
0.47-µH inductor gives the same output voltage ripple as operating with 1.4 MHz using 1-µH inductor.

Equation 3. GUID-87FEAFCC-F4FE-4F35-A1D3-0FDAE2CC7AC7-low.gif

In power save mode the output voltage rises slightly above the nominal output voltage in PWM mode, as shown in Figure 8-8 and Figure 8-9. This effect is reduced by increasing the output capacitance or the inductor value. This effect is also reduced by programming the output voltage of the TPS62090Q lower than the target value. As an example, if the target output voltage is 3.3 V, then the TPS62090Q is programmed to 3.3 V – 0.8%. As a result the output voltage accuracy is now –2.2% to +2.2% instead of –1.4% to 3%. The output voltage accuracy in PFM operation is reflected in the Section 6.5 table and given for a 22-µF output capacitance.