SLVSAW2C March   2012  – October 2016 TPS62090 , TPS62091 , TPS62092 , TPS62093

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable and Disable (EN)
      2. 8.3.2  Softstart (SS) and Hiccup Current Limit During Startup
      3. 8.3.3  Voltage Tracking (SS)
      4. 8.3.4  Short Circuit Protection (Hiccup-Mode)
      5. 8.3.5  Output Discharge Function
      6. 8.3.6  Power Good Output (PG)
      7. 8.3.7  Frequency Set Pin (FREQ)
      8. 8.3.8  Undervoltage Lockout (UVLO)
      9. 8.3.9  Thermal Shutdown
      10. 8.3.10 Charge Pump (CP, CN)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Width Modulation Operation
      2. 8.4.2 Power Save Mode Operation
      3. 8.4.3 Low Dropout Operation (100% Duty Cycle)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input and Output Capacitor Selection
        3. 9.2.2.3 Setting the Output Voltage
        4. 9.2.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guideline
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guideline

  • It is recommended to place the input capacitor as close as possible to the IC pins PVIN and PGND.
  • The VOS connection is noise sensitive and needs to be routed as short and directly to the output pin of the inductor.
  • The exposed thermal pad of the package, analog ground (pin 6) and power ground (pin 14, 15) should have a single joint connection at the exposed thermal pad of the package. This minimizes switch node jitter.
  • The charge pump capacitor connected to CP and CN should be placed close to the IC to minimize coupling of switching waveforms into other traces and circuits.
  • Refer to Figure 29 and the evaluation module User Guide (SLVU670) for an example of component placement, routing and thermal design.

11.2 Layout Example

TPS62090 TPS62091 TPS62092 TPS62093 TPS62090_PCBLayout.gif Figure 29. TPS6209x Layout