SLVSAQ5E March   2012  – May 2017 TPS62125

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout
      2. 7.3.2 Enable Comparator (EN / EN_hys)
      3. 7.3.3 Power Good Output and Output Discharge (PG)
      4. 7.3.4 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse Width Modulation (PWM) Operation
      2. 7.4.2 Power-Save Mode
      3. 7.4.3 100% Duty Cycle Low Dropout Operation
      4. 7.4.4 Soft-Start
      5. 7.4.5 Short-Circuit Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Setting
        2. 8.2.2.2 Enable Threshold and Hysteresis Setting
        3. 8.2.2.3 Power Good (PG) Pullup and Output Discharge Resistor
        4. 8.2.2.4 Output Filter Design (Inductor and Output Capacitor)
        5. 8.2.2.5 Inductor Selection
        6. 8.2.2.6 Output Capacitor Selection
        7. 8.2.2.7 Input Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 TPS62125 5-V Output Voltage Configuration
      2. 8.3.2 TPS62125 5-V VOUT
      3. 8.3.3 TPS62125 Operation From a Storage Capacitor Charged From a 0.5 mA Current Source
      4. 8.3.4 5 V to -5 V Inverter Configuration
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

(1)
MIN MAX UNIT
Pin voltage(2) VIN –0.3 20 V
SW (DC) –0.3 VIN + 0.3V V
SW (AC, less than 10ns)(3) -3.0 23.5 V
EN –0.3 VIN + 0.3 V
FB –0.3 3.6 V
VOS, PG –0.3 12 V
EN_hys –0.3 7 V
Power good sink current IPG 10 mA
EN_hys sink current IEN_hys 3 mA
Maximum operating junction temperature, TJ –40 125 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal GND.
(3) While switching

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VIN Supply voltage 3 17 V
Output current capability 3 V ≤ VIN < 6 V 200 mA
6 V ≤ VIN ≤ 17 V 300
TA Operating ambient temperature (1) (Unless Otherwise Noted) –40 85 °C
TJ Operating junction temperature, –40 125 °C
(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)) and the maximum power dissipation of the device in the application (PD(max)); for more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TPS62125 UNIT
DSG (WSON)
8 PINS
RθJA Junction-to-ambient thermal resistance 65.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 93.3 °C/W
RθJB Junction-to-board thermal resistance 30.1 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 47.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 7.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted), VIN = 12 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input voltage range(1) 3 17 V
VOUT Output voltage range 1.2 10 V
IQ Quiescent current IOUT = 0 mA, device not switching, EN = VIN, regulator sleeps 13 23 µA
IOUT = 0 mA, device switching, VIN = 7.2 V,
VOUT = 1.2 V, L = 22 µH		 14 µA
VIN = 5 V, EN = 1.1 V, enable comparator active, device DC/DC converter off 6 11 µA
IActive Active mode current consumption VIN = 5 V = VOUT, TA = 25°C, high-side MOSFET switch fully turned on (100% mode) 230 275 µA
ISD Shutdown current(2) Enable comparator off, EN < 0.4 V,
VOUT = SW = 0 V, VIN = 5 V 		0.35 2.4 µA
VUVLO Undervoltage lockout threshold Falling VIN 2.8 2.85 V
Rising VIN 2.9 2.95 V
ENABLE COMPARATOR THRESHOLD AND HYSTERESIS (EN, EN_hys)
VTH EN ON EN pin threshold rising edge 3 V ≤ V≤ 17 V 1.16 1.20 1.24 V
VTH EN OFF EN pin threshold falling edge 1.12 1.15 1.19 V
VTH EN Hys EN pin hysteresis IN 50 mV
IIN EN Input bias current into EN pin EN = 1.3 V 0 50 nA
VEN_hyst EN_hys pin output low IEN_hyst = 1 mA, EN = 1.1 V 0.4 V
IIN EN_hyst Input bias current into EN_hyst pin EN_hyst = 1.3 V 0 50 nA
POWER SWITCH
RDS(ON) High-side MOSFET ON-resistance VIN = 3 V, I = 100 mA 2.4 4 Ω
VIN = 12 V, I = 100 mA 1.5 2.6
Low-side MOSFET ON-resistance VIN = 3 V, I = 100 mA 0.75 1.3
VIN = 12 V, I = 100 mA 0.6 1
ILIMF Switch current limit high-side MOSFET VIN = 12 V 600 750 900 mA
TSD Thermal shutdown Increasing junction temperature 150 °C
Thermal shutdown hysteresis Decreasing junction temperature 20 °C
OUTPUT
tONmin Minimum ON-time VIN = 5 V, VOUT = 2.5 V 500 ns
tOFFmin Minimum OFF-time VIN = 5 V 60 ns
VREF_FB Internal reference voltage of error amplifier 0.808 V
VFB Feedback voltage accuracy Referred to internal reference (VREF_FB) –2.5% 0% 2.5%
Feedback voltage line regulation IOUT = 100 mA, 5 V ≤ VIN ≤ 17 V, VOUT = 3.3 V(3) –0.05 %/V
Feedback voltage load regulation VOUT = 3.3 V; IOUT = 1 mA to 300 mA, VIN = 12 V(3) –0.004 %/mA
IIN_FB Input bias current into FB pin VFB = 0.8 V 0 50 nA
tStart Regulator start-up time Time from EN high to device starts switching,
VIN = 5 V		 50 µs
tRamp Output voltage ramp time Time to ramp up VOUT = 1.8 V, no load 200
ILK_SW Leakage current into SW pin(4) VOS = VIN = VSW = 1.8 V, EN = GND, device in shutdown mode 1.8 2.85 µA
IIN_VOS Bias current into VOS pin 0 50 nA
POWER GOOD OUTPUT (PG)
VTH_PG Power good threshold voltage Rising VFB feedback voltage 93% 95% 97%
Falling VFB feedback voltage 87% 90% 93%
VOL PG pin output low voltage Current into PG pin IPG= 0.4 mA 0.3 V
VOH PG pin output high voltage Open drain output, external pullup resistor 10 V
IIN_PG Bias current into PG pin V(PG) = 3 V, EN = 1.3 V, FB = 0.85 V 0 50 nA
(1) The part is functional down to the falling UVLO (Undervoltage Lockout) threshold
(2) Current into VIN pin
(3) VOUT = 3.3 V, L = 15 µH, COUT = 10 µF
(4) An internal resistor divider network with typ. 1 MΩ total resistance is connected between SW pin and GND.

6.6 Typical Characteristics

TPS62125 ISD.gif Figure 1. Shutdown Current vs. Input Voltage
TPS62125 IQ_vs_rising_VEN_6V_12V.gif Figure 3. Quiescent Current vs. EN Voltage, Rising VEN
TPS62125 VTEN.gif Figure 5. EN Comparator Thresholds vs. Input Voltage
TPS62125 RDSON_LS.gif Figure 7. RDSON Low-Side Switch (Rectifier)
TPS62125 Iq_VS_VIN_VST.gif Figure 2. Quiescent Current vs. Input Voltage
TPS62125 IQ_vs_falling_VEN_6V_12V.gif Figure 4. Quiescent Current vs. VEN Voltage, Falling VEN
TPS62125 RDSON_HS.gif Figure 6. RDSON High-Side Switch