SLVSC52B July   2013  – September 2015 TPS62152-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Pulse-Width Modulation (PWM) Operation
      2. 7.3.2  100% Duty-Cycle Operation
      3. 7.3.3  Enable / Shutdown (EN)
      4. 7.3.4  Soft Start or Tracking (SS/TR)
      5. 7.3.5  Current-Limit and Short-Circuit Protection
      6. 7.3.6  Power Good (PG)
      7. 7.3.7  Pin-Selectable Output Voltage (DEF)
      8. 7.3.8  Frequency Selection (FSW)
      9. 7.3.9  Undervoltage Lockout (UVLO)
      10. 7.3.10 Thermal Shutdown
      11. 7.3.11 Tracking Function
      12. 7.3.12 Feedback Pin (FB)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Save Mode Operation
      2. 7.4.2 Active Output Discharge
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Component Selection
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Output Capacitor
            1. 8.2.2.1.2.1 Input Capacitor
            2. 8.2.2.1.2.2 Soft-Start Capacitor
        2. 8.2.2.2 Output Filter and Loop Stability
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGT Package
16-Pin VQFN With Exposed Thermal Pad
Top View

Pin Functions

PIN(1) TYPE(2) DESCRIPTION
NAME NO.
AGND 6 G Analog ground. Connected AGND directly to the exposed thermal pad and common ground plane.
AVIN 10 S Supply voltage for control circuitry. Connect to the same source as PVIN.
DEF 8 I Output voltage scaling (Low = nominal, High = nominal + 5%)(4)
EN 13 I Enable input (High = enabled, Low = disabled)(4)
FB 5 I TI recommends connecting FB to AGND for improved thermal performance.
FSW 7 I Switching frequency select (Low ≈ 2.5 MHz, High ≈ 1.25 MHz(3) for typical operation)(4)
PG 4 O Output power good (High = VOUT ready, Low = VOUT below nominal regulation); open drain (requires pullup resistor; goes high-impedance when device is switched off)
PGND 15 G Power ground. Must be connected directly to the exposed thermal pad and common ground plane.
16
PVIN 11 S Supply voltage for power stage. Connect to same source as AVIN.
12
SS/TR 9 I Soft-start or tracking pin. An external capacitor connected to this pin sets the internal voltage-reference rise time. The pin can be used for tracking and sequencing.
SW 1 O Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and output capacitor.
2
3
VOS 14 I Output-voltage sense pin and connection for the control-loop circuitry.
Exposed thermal pad — Connect to AGND (pin 6), PGND (pins 15,16) and common ground plane(5). Solder to PCB to achieve appropriate power dissipation and mechanical reliability.
(1) For more information about connecting pins, see Detailed Description and Application Information sections.
(2) G = ground, S = supply, I = input, O = output
(3) Connect FSW to VOUT or PG in this case.
(4) An internal pulldown resistor keeps the logic level low, if the pin is floating.
(5) See Figure 37.