SLVSBB8B August   2014  – May 2017 TPS62180 , TPS62182

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable / Shutdown (EN)
      2. 8.3.2 Soft Start / Tracking (SS/TR)
      3. 8.3.3 Power Good (PG)
      4. 8.3.4 Undervoltage Lockout (UVLO)
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode (PSM) Operation
      3. 8.4.3 Minimum Duty Cycle and 100% Mode Operation
      4. 8.4.4 Automatic Efficiency Enhancement (AEE)
      5. 8.4.5 Phase-Shifted Operation
      6. 8.4.6 Current Limit, Current Balancing, and Short Circuit Protection
      7. 8.4.7 Tracking
      8. 8.4.8 Operation with Fixed VOUT
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical TPS62180 Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Programming the Output Voltage
          3. 9.2.1.2.3 Output Filter Selection
          4. 9.2.1.2.4 Inductor Selection
          5. 9.2.1.2.5 Output Capacitor Selection
          6. 9.2.1.2.6 Input Capacitor Selection
          7. 9.2.1.2.7 Soft Start Capacitor Selection
        3. 9.2.1.3 Application Performance Curves
      2. 9.2.2 TPS62180 Low Profile Solution
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Inductor
          2. 9.2.2.2.2 Input and Output Capacitors
          3. 9.2.2.2.3 Soft Start Capacitor
          4. 9.2.2.2.4 Using the Accurate EN Threshold
        3. 9.2.2.3 Application Performance Curves
    3. 9.3 TPS62180 Output Voltage Application Examples
      1. 9.3.1 Application Schematic Examples
      2. 9.3.2 Design Requirements
      3. 9.3.3 External Component Selection
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Links
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Pin voltage range(2) VIN1, VIN2 –0.3 17 V
EN, PG –0.3 VIN + 0.3 V
SW1, SW2, (DC) –0.3 VIN + 0.3 V
SW1, SW2, (AC, less than 10ns)(3) –2 24.5
SS/TR –0.3 VIN + 0.3,
but ≤ 7		 V
FB, VO –0.3 7 V
Power good sink current PG 10 mA
Operating junction temperature range TJ –40 150 °C
Storage Temperature Range Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground pin.
(3) While switching.

7.2 ESD Ratings

MIN MAX UNIT
VESD(1) Human Body Model (HBM) ESD stress voltage(2) –1 1 kV
Charge device model (CDM) ESD stress voltage –0.5 0.5
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN TYP MAX UNIT
Supply voltage range, VIN 4 15 V
Output voltage range, VOUT 0.9 6 V
Maximum Output current, IOUT(max) 0.9V ≤ VOUT ≤ 3.3V 6 A
3.3V < VOUT 6
Operating junction temperature, TJ –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TPS6218x UNIT
YZF (24 PINS)
RθJA Junction-to-ambient thermal resistance 61.5 °C/W
RθJCtop Junction-to-case (top) thermal resistance 0.3 °C/W
RθJB Junction-to-board thermal resistance 10.1 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter 10.1 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance n/a °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Over operating junction temperature range (TJ = –40°C to +125°C) and VIN = 4 V to 15 V.
Typical values at VIN = 12 V and TJ = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input voltage range 4 15 V
IQ Operating quiescent current EN = High, IOUT = 0 mA, Device not switching,
(TJ = –40°C to +85°C)		 28 55 µA
ISD Shutdown current EN = Low (≤ 0.3 V), (TJ = –40°C to +85°C) 2.8 15 µA
VUVLO Undervoltage lockout threshold (1) Falling input voltage 3.5 3.6 3.7 V
Hysteresis 300 mV
TSD Thermal shutdown Rising junction temperature 160 °C
Hysteresis 20
CONTROL (EN, SS/TR, PG)
VH_EN High-level input threshold voltage (EN) 0.97 1 1.03 V
VL_EN Low-level input threshold voltage (EN) 0.87 0.9 0.93 V
ILKG_EN Input leakage current (EN) EN = VIN or GND 0.01 1.2 µA
ISS/TR SS/TR pin source current 4.5 5 5.5 µA
VTH_PG Power good threshold voltage Rising (%VOUT) 94% 96% 98%
Falling (%VOUT) 90% 92% 94%
VOL_PG Power good output low voltage IPG= -2 mA 0.3 V
ILKG_PG Input leakage current (PG) 1 100 nA
POWER SWITCH
RDS(ON) High-side MOSFET ON-resistance VIN = 7.5 V Phase 1 27 65 mΩ
Phase 2
Low-side MOSFET ON-resistance Phase 1 21 45 mΩ
Phase 2
ILIM High-side MOSFET current limit Each phase, VIN = 7.5 V 4.0 4.7 5.5 A
TPSD Phase shift delay time Phase 2 after Phase 1, PWM mode 250 ns
OUTPUT
VREF Internal reference voltage 0.792 0.8 0.808 V
ILKG_FB Input leakage current (FB) VFB = 0.8 V 1 100 nA
RDISCHARGE Output discharge resistance EN = Low 60 Ω
VOUT Output voltage range (TPS62180) VIN ≥ VOUT 0.9 6 V
Output voltage (TPS62182) 3.3 V
Feedback voltage accuracy
(TPS62180)(2)		 PWM Mode, VIN ≥ VOUT + 1 V –1% 1%
Power Save Mode, VOUT = 3.3 V, Iload ≥ 1 mA,
L = 1 µH, COUT = 2 x 47 µF, (TJ = –40°C to +85°C)		 –1% 2%
Power Save Mode, VOUT = 1.8 V, Iload ≥ 1 mA,
L = 1 µH, COUT = 4 x 47 µF, (TJ = –40°C to +85°C)
Power Save Mode, VOUT = 0.9 V, Iload ≥ 1 mA,
L = 1 µH, COUT = 4 x 47 µF, (TJ = –40°C to +85°C)		 –1% 3%
Output voltage accuracy
(TPS62182)(2)		 PWM Mode, VIN ≥ VOUT + 1 V –1% 1%
Power Save Mode, Iload ≥ 1 mA, L = 1 µH,
COUT = 2 x 47 µF, (TJ = –40°C to +85°C)		 –1% 2%
Load regulation VOUT = 3.3 V, PWM Mode operation 0.04 %/A
Line regulation 4 V ≤ VIN ≤ 15 V, VOUT = 3.3 V, IOUT = 4 A 0.01 %/V
tHICCUP Hiccup on time 0.9 ms
Hiccup off time 5
(1) The minimum VIN value of 4 V is not violated by UVLO threshold and hysteresis variations.
(2) The accuracy in Power Save Mode can be improved by increasing the output capacitor value, reducing the output voltage ripple.

7.6 Typical Characteristics

TPS62180 TPS62182 SLVSBB8_IQ.gif
Figure 1. Quiescent Current
TPS62180 TPS62182 SLVSBB8_RDSONHS.gif
Figure 3. High-Side Switch Resistance
TPS62180 TPS62182 SLVSBB8_ISD.gif
Figure 2. Shutdown Current
TPS62180 TPS62182 SLVSBB8_RDSONLS.gif
Figure 4. Low-Side Switch Resistance