SLVSB63A December 2011 – March 2016 TPS62231-Q1 , TPS622314-Q1
PRODUCTION DATA.
The TPS6223x-Q1 device family is a high-frequency, synchronous step-down DC-DC converter ideal for space-optimized automotive and industrial applications. The device supports up to 500-mA output current and allows the use of tiny and low-cost chip inductors and capacitors.
With a wide input-voltage range of 2.05 V to 6 V, the device can be powered by a preregulated voltage rail or Li-Ion batteries with extended voltage range. Two different fixed-output voltage versions are available at 1.5 V and 1.8 V.
The TPS6223x-Q1 series features switch frequency up to 3.8 MHz. At medium to heavy loads, the converter operates in PWM mode and automatically enters Power Save Mode operation at light load currents to maintain high efficiency over the entire load current range.
Because of its excellent PSRR and AC load regulation performance, the device is also suitable to replace linear regulators to obtain better power conversion efficiency.
The Power Save Mode in TPS6223x-Q1 reduces the quiescent current consumption down to 22 μA during light load operation. It is optimized to achieve very low output voltage ripple even with small external component and features excellent AC load regulation.
For noise-sensitive applications, the device can be forced to PWM Mode operation over the entire load range by pulling the MODE pin high. In the shutdown mode, the current consumption is reduced to less than 1 μA. The TPS6223x-Q1 is available in a 1-mm × 1.5-mm2 6-pin SON package.
PART NUMBER | OUTPUT VOLTAGE |
FREQUENCY |
---|---|---|
TPS62231-Q1 | 1.8 V | 3 MHz |
TPS622314-Q1 | 1.5 V | 3 MHz |
Changes from * Revision (December 2011) to A Revision
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | MODE | IN | When the MODE pin is high, the device is forced to operate in PWM mode. When the MODE pin is low, the power save mode is enabled with automatic transition from PFM (pulse frequency mode) to PWM (pulse width modulation) mode. This pin must be terminated. |
2 | SW | OUT | This pin is the switch pin and is connected to the internal MOSFET switches. Connect the inductor to this pin. |
3 | VIN | PWR | VIN power supply pin. |
4 | GND | PWR | GND supply pin. |
5 | EN | IN | This is the enable pin of the device. Pulling this pin to low forces the device into shutdown mode. Pulling this pin to high enables the device. This pin must be terminated. |
6 | FB | IN | Feedback pin for the internal regulation loop. Connect this pin directly to the output capacitor. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VI | Voltage at VIN and SW pin(2) | –0.3 | 7 | V | |
Voltage at EN, MODE pin(2) | –0.3 | (VIN + 0.3) ≤7 | V | ||
Voltage at FB pin(2) | –0.3 | 3.6 | V | ||
Peak output current | internally limited | A | |||
Power dissipation | Internally limited | ||||
TJ | Maximum operating junction temperature | –40 | 125 | °C | |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2000 | V |
Charged-device model (CDM), per AEC Q100-011 | ±1000 | |||
Machine Model (MM) | 200 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
Supply voltage, VIN(4) | 2.05 | 6 | V | |||
Effective output inductance | 0.7 | 1 or 2.2 | 4.3 | μH | ||
Effective output capacitance | 2 | 4.7 | 15 | μF | ||
Recommended minimum supply voltage | VOUT ≤ (VIN – 1 V)(2) | 500-mA maximum IOUT(3) | 3 | 3.6 | V | |
350-mA maximum IOUT(3) | 2.5 | 2.7 | ||||
VOUT ≤ 1.8 V | 60-mA maximum output current(3) | 2.05 | ||||
Operating junction temperature, TJ | –40 | 125 | °C | |||
Ambient temperature, TA | –40 | 105 | °C |
THERMAL METRIC(1) | TPS62231x-Q1 | UNIT | |
---|---|---|---|
DRY (SON) | |||
6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 294.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 166.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 166.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 27.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 159.9 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SUPPLY | |||||||
VIN | Input voltage range(5) | 2.05 | 6 | V | |||
IQ | Operating quiescent current | IOUT = 0 mA. PFM mode enabled (MODE = 0) device not switching |
22 | 40 | μA | ||
IOUT = 0 mA. PFM mode enabled (MODE = 0) device switching, VIN = 3.6 V, VOUT = 1.2 V |
25 | μA | |||||
IOUT = 0 mA. Switching with no load (MODE/DATA = VIN), PWM operation, VOUT = 1.8 V, L = 2.2 μH |
3 | mA | |||||
ISD | Shutdown current | EN = GND(3) | 0.1 | 1 | μA | ||
UVLO | Undervoltage-lockout threshold | Falling | 1.8 | 1.9 | V | ||
Rising | 1.9 | 2.05 | V | ||||
ENABLE, MODE THRESHOLD | |||||||
VIH TH | Threshold for detecting high EN, MODE | 2.05 V ≤ VIN ≤ 6 V , rising edge | 0.8 | 1 | V | ||
VIL TH HYS | Threshold for detecting low EN, MODE | 2.05 V ≤ VIN ≤ 6 V , falling edge | 0.4 | 0.6 | V | ||
IIN | Input bias Current, EN, MODE | EN, MODE = GND or VIN = 3.6 V | 0.01 | 0.5 | μA | ||
POWER SWITCH | |||||||
RDS(ON) | High-side MOSFET on-resistance | VIN = 3.6 V, TJmax = 105°C; RDS(ON) max value | 600 | 850 | mΩ | ||
Low-side MOSFET on-resistance | VIN = 3.6 V, TJmax = 105°C; RDS(ON) max value | 350 | 480 | ||||
ILIMF | Forward current-limit MOSFET high side | VIN = 3.6 V, open loop | 690 | 850 | 1050 | mA | |
Forward current-limit MOSFET low side | VIN = 3.6 V, open loop | 550 | 840 | 1220 | mA | ||
TSD | Thermal shutdown | Increasing junction temperature | 150 | °C | |||
Thermal shutdown hysteresis | Decreasing junction temperature | 20 | °C | ||||
CONTROLLER | |||||||
tONmin | Minimum on time | VIN = 3.6 V, VOUT = 1.8 V, Mode = high, IOUT = 0 mA | 135 | ns | |||
tOFFmin | Minimum off time | 40 | ns | ||||
OUTPUT | |||||||
VREF | Internal reference voltage | 0.70 | V | ||||
VOUT | Output voltage accuracy(1) | VIN = 3.6 V, Mode = GND, device operating in PFM Mode, IOUT = 0 mA | 0% | ||||
VIN = 3.6 V, MODE = VIN, IOUT = 0 mA |
TA = 25°C | –2% | 2% | ||||
TA = –40°C to 105°C | –2.5% | 2.5% | |||||
DC output voltage load regulation | PWM operation, Mode = VIN = 3.6 V, VOUT = 1.8 V | 0.001 | %/mA | ||||
DC output voltage line regulation | IOUT = 0 mA, Mode = VIN, 2.05 V ≤ VIN ≤ 6 V | 0 | %/V | ||||
tStart | Start-up time | Time from active EN to VOUT = 1.8 V, VIN = 3.6 V, 10-Ω load |
100 | μs | |||
ILK_SW | Leakage current into SW pin | VIN = VOUT = VSW = 3.6 V, EN = GND(2) | 0.1 | 0.5 | μA |
The TPS6223x-Q1 synchronous step-down converter family of devices includes a unique, hysteretic PWM-controller scheme which enables switch frequencies over 3 MHz, excellent transient and AC load regulation, and operation with cost-competitive external components.
The controller topology supports forced PWM mode as well as power save mode operation. power save mode operation reduces the quiescent current consumption down to 22 μA and ensures high conversion efficiency at light loads by skipping switch pulses. In forced PWM mode, the device operates on a quasi-fixed frequency, avoids pulse skipping, and allows filtering of the switch noise by external filter components. The actual switching frequency depends on the input voltage, output voltage, device mode, and actual load current.
The TPS6223x-Q1 family of devices offers fixed output-voltage options featuring smallest solution size by using only three external components.
The internal switch-current limit of 850 mA (typical) supports output currents of up to 500 mA, depending on the operating condition.
A significant advantage of TPS6223x-Q1 family of devices compared to other hysteretic PWM controller topologies is excellent DC and AC load regulation capability in combination with low output-voltage ripple over the entire load range which makes this device well suited for audio and RF applications.
When the output voltage falls below the threshold of the error comparator, a switch pulse is initiated, and the high-side switch is turned on. This switch remains on until a minimum on time of tONmin expires and the output voltage trips the threshold of the error comparator or the inductor current reaches the high-side switch-current limit. When the high-side switch turns off, the low-side switch rectifier is turned on and the inductor current ramps down until the high side switch turns on again or the inductor current reaches zero.
In forced PWM mode operation, the negative inductor current is allowed to enable continuous conduction mode even at no load condition.
The undervoltage-lockout (UVLO) circuit prevents the device from misoperation at low input voltages. This circuit prevents the converter from turning on the switch or rectifier MOSFET under undefined conditions. The TPS6223x-Q1 family of devices has an UVLO threshold set to 1.8 V (typical). Fully-functional operation is permitted for the input voltage down to the falling UVLO-threshold level. The converter starts operation again when the input voltage crosses the rising UVLO-threshold level.
The device starts operation when the EN pin is set high and starts up with the soft-start as previously described. For proper operation, the EN pin must be terminated and must not be left floating.
Pulling the EN pin low forces the device into shutdown, with a shutdown quiescent current of 0.1 μA (typical). In this mode, the P and N-channel MOSFETs are turned off, the internal resistor feedback divider is disconnected, and the entire internal-control circuitry is switched off.
The EN input can be used to control power sequencing in a system with various DC-DC converters. The EN pin can be connected to the output of another converter, to drive the EN pin high and getting a sequencing of supply rails.
As soon as the junction temperature, TJ, exceeds 150°C (typical), the device goes into thermal shutdown. In this mode, the high-side and low-side MOSFETs are turned off. The device continues operation when the junction temperature falls below the thermal shutdown hysteresis.
The device has an internal soft-start circuit that controls the ramp up of the output voltage and limits the inrush current during start-up. This limits input voltage drops when a battery or a high-impedance power source is connected to the input of the converter.
The soft-start system generates a monotonic ramp up of the output voltage and reaches the nominal output voltage which is typically 100 μs after EN pin was pulled high.
If the output voltage does not reach the target value by this time, such as in the case of heavy load, the converter then operates in a current limit mode set by the switch-current limits.
The device is able to start into a prebiased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage to the nominal value.
Connecting the MODE pin to GND enables the automatic PWM mode and power save mode operation. The converter operates in quasi-fixed frequency PWM mode at moderate to heavy loads and in the PFM (pulse frequency modulation) mode during light loads, which maintains high efficiency over a wide-load current range. In PFM mode, the device starts to skip switch pulses and generates only single pulses with an on time of tONmin. The PFM Mode frequency depends on the load current and the external inductor and output capacitor values. The PFM mode of the device is optimized for low output-voltage ripple if small external components are used. Even at low output currents, the PFM frequency is above the audible noise spectrum and makes this operation mode suitable for audio applications.
Use Equation 1 to estimate the on time tONmin.
where
Therefore, use Equation 2 to calculate the approximate peak inductor current in PFM mode.
where
Use Equation 3 to estimate the transition from PFM into PWM mode and from PWM into PFM.
where
Pulling the MODE pin high forces the converter to operate in a continuous-conduction PWM mode even at light load currents. The advantage is that the converter operates with a quasi-fixed frequency that allows simple filtering of the switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power save mode during light loads.
For additional flexibility, switch from power save mode to forced PWM mode during operation. This switching allows for efficient power management by adjusting the operation of the converter to the specific system requirements.
The device starts to enter 100% duty-cycle mode when the input voltage comes close to the nominal output voltage. To maintain the output voltage, the high-side switch is turned on 100% for one or more cycles.
With further decreasing VIN, the high-side MOSFET switch is turned on completely. In this case the converter offers a low input-to-output voltage difference which is particularly useful in battery-powered applications to achieve the longest operation time by taking full advantage of the whole battery voltage range.
Use Equation 4 to calculate the minimum input voltage to maintain regulation which is dependent on the load current and output voltage.
where
The device integrates a high-side and low-side MOSFET current limit to protect the device against heavy load or short circuit. The current in the switches is monitored by current-limit comparators. When the current in the P-channel MOSFET reaches the current limit, the P-channel MOSFET is turned off and the N-channel MOSFET is turned on to ramp down the current in the inductor. The high-side MOSFET switch can only turn on again when the current in the low-side MOSFET switch has decreased below the threshold of the current-limit comparator.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS6223x-Q1 family of devices is a high-frequency, synchronous, step-down DC-DC converter providing switch frequencies up to 3.8 MHz.
The device operates over an input voltage range of 2.05 V to 6 V. The TPS62231-Q1 device has a fixed output voltage of 1.8 V (typical) and the TPS622314-Q1 device has a fixed output voltage of 1.5 V (typical). The device is easy to use and requires just three external components; however, the selection of external components and PCB layout must comply with the design guidelines to achieve the specified performance.
The device is optimized to operate with effective inductance values in the range of 0.7 μH to 4.3 μH and with effective output capacitance in the range of 2 μF to 15 μF. The internal compensation is optimized to operate with an output filter of L = 1 μH or 2.2 μH and COUT = 4.7 μF. Larger or smaller inductor and capacitor values can be used to optimize the performance of the device for specific operation conditions. For more details, see the Checking Loop Stability section.
The inductor value affects the peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage ripple, and the efficiency. The selected inductor must be rated for DC resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VIN or VOUT. Use Equation 5 to calculate the maximum inductor current under static load conditions. The saturation current of the inductor must be rated higher than the maximum inductor current as calculated with Equation 6. This rating is recommended because during heavy load transient the inductor current will rise above the calculated value.
where
where
In high-frequency converter applications, the efficiency is essentially affected by the inductor AC resistance (essentially the quality factor) and to a smaller extent by the inductor DCR value. To achieve high efficiency operation, use care when selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor size, increased inductance usually results in an inductor with lower saturation current.
The total losses of the coil consist of both the losses in the DC resistance, R(DC), and the following frequency-dependent components:
Table 1 lists the inductor series from different suppliers that have been used with the TPS6223x-Q1 converters. These components must be verified and validated to determine whether the component is suitable for the end application.
INDUCTANCE (μH) |
DIMENSIONS (mm3) |
INDUCTOR TYPE | SUPPLIER |
---|---|---|---|
1 | 2.5 × 2 × 1.2 | LQM2HPN1R0MJ0 | Murata |
2.2 | 2 × 1.2 × 0.55 | LQM21PN2R2 | Murata |
1 or 2.2 | 2 × 1.2 × 1 | KSLI2012 series | Hitachi Metal |
The unique hysteretic PWM control scheme of the TPS6223x-Q1 device allows the use of tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies.
At light load currents the converter operate in power save mode and the output voltage ripple is dependent on the output capacitor value and the PFM peak inductor current. Higher output capacitor values minimize the voltage ripple in PFM Mode and tighten DC output accuracy in PFM Mode.
Because of the nature of the buck converter having a pulsating input current, a low-ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For most applications a 2.2-μF to 4.7-μF ceramic capacitor is recommended. The input capacitor can be increased without any limit for better input voltage filtering. Because a ceramic capacitor loses up to 80% of the initial capacitance at 5 V, TI recommends using 4.7-μF input capacitors for input voltages greater than 4.5 V.
Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on the input can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even damage the part by exceeding the maximum ratings.
Table 2 lists some tested input and output capacitors. These components must be verified and validated to determine whether the component is suitable for the end application.
CAPACITANCE (μF) | SIZE | CAPACITOR TYPE | SUPPLIER |
---|---|---|---|
2.2 | 0402 | GRM155R60J225 | Murata |
4.7 | 0402 | AMK105BJ475MV | Taiyo Yuden |
4.7 | 0402 | GRM155R60J475 | Murata |
4.7 | 0402 | CL05A475MQ5NRNC | Samsung |
4.7 | 0603 | GRM188R60J475 | Murata |
The first step of circuit and stability evaluation is to look at the following signals from a steady-state perspective:
These signals are the basic signals that must be measured when evaluating a switching converter. When the switching waveform shows large duty-cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. This is often a result of board layout, L-C combination, or both.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between the application of the load transient and the turnon of the P-channel MOSFET, the output capacitor must supply all of the current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) × ESR, where ESR is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge CO generating a feedback error signal used by the regulator to return VOUT to the steady-state value. The results are most easily interpreted when the device operates in PWM mode.
During this recovery time, VOUT can be monitored for settling time, overshoot, or ringing that helps judge the stability of the converter. Without any ringing, the loop has usually more than 45° of phase margin.
Because the damping factor of the circuitry is directly related to several resistive parameters (for example, MOSFET rDS(on)) that are temperature dependant, the loop stability analysis must occur over the input voltage range, load current range, and temperature range.
The TPS6223x-Q1 family of devices has no special requirements for the input power supply. The output current of the input power supply must to be rated according to the supply voltage, output voltage, and output current of the TPS6223x-Q1 family of devices.
As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Use care when designing the board layout to get the specified performance. If the layout is not done carefully, the regulator could show poor line regulation, load regulation, stability issues, and EMI problems. Providing a low-inductance, low-impedance ground path is critical. Therefore, use wide and short traces for the main current paths. Place the input capacitor as close as possible to the IC pins as well as the inductor and output capacitor.
Use a common power GND node and a different node for the Signal GND to minimize the effects of ground noise. Keep the common path to the GND PIN, which returns the small signal components and the high current of the output capacitors as short as possible to avoid ground noise. Connect the FB line to the output capacitor and route the line away from noisy components and traces (for example, SW line).
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.
PARTS | PRODUCT FOLDER | SAMPLE & BUY | TECHNICAL DOCUMENTS | TOOLS & SOFTWARE | SUPPORT & COMMUNITY |
---|---|---|---|---|---|
TPS62231-Q1 | Click here | Click here | Click here | Click here | Click here |
TPS622314-Q1 | Click here | Click here | Click here | Click here | Click here |
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.