SLVSB63A December   2011  – March 2016 TPS62231-Q1 , TPS622314-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 pPin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout
      2. 7.3.2 Enable and Shutdown
      3. 7.3.3 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Soft Start
      2. 7.4.2 Power Save Mode
      3. 7.4.3 Forced PWM Mode
      4. 7.4.4 100% Duty-Cycle Low-Dropout Operation
      5. 7.4.5 Short-Circuit Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Filter Design (Inductor and Output Capacitor)
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Checking Loop Stability
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resource
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The TPS6223x-Q1 synchronous step-down converter family of devices includes a unique, hysteretic PWM-controller scheme which enables switch frequencies over 3 MHz, excellent transient and AC load regulation, and operation with cost-competitive external components.

The controller topology supports forced PWM mode as well as power save mode operation. power save mode operation reduces the quiescent current consumption down to 22 μA and ensures high conversion efficiency at light loads by skipping switch pulses. In forced PWM mode, the device operates on a quasi-fixed frequency, avoids pulse skipping, and allows filtering of the switch noise by external filter components. The actual switching frequency depends on the input voltage, output voltage, device mode, and actual load current.

The TPS6223x-Q1 family of devices offers fixed output-voltage options featuring smallest solution size by using only three external components.

The internal switch-current limit of 850 mA (typical) supports output currents of up to 500 mA, depending on the operating condition.

A significant advantage of TPS6223x-Q1 family of devices compared to other hysteretic PWM controller topologies is excellent DC and AC load regulation capability in combination with low output-voltage ripple over the entire load range which makes this device well suited for audio and RF applications.

When the output voltage falls below the threshold of the error comparator, a switch pulse is initiated, and the high-side switch is turned on. This switch remains on until a minimum on time of tONmin expires and the output voltage trips the threshold of the error comparator or the inductor current reaches the high-side switch-current limit. When the high-side switch turns off, the low-side switch rectifier is turned on and the inductor current ramps down until the high side switch turns on again or the inductor current reaches zero.

In forced PWM mode operation, the negative inductor current is allowed to enable continuous conduction mode even at no load condition.

7.2 Functional Block Diagram

TPS62231-Q1 TPS622314-Q1 fbd_slvsb63.gif

7.3 Feature Description

7.3.1 Undervoltage Lockout

The undervoltage-lockout (UVLO) circuit prevents the device from misoperation at low input voltages. This circuit prevents the converter from turning on the switch or rectifier MOSFET under undefined conditions. The TPS6223x-Q1 family of devices has an UVLO threshold set to 1.8 V (typical). Fully-functional operation is permitted for the input voltage down to the falling UVLO-threshold level. The converter starts operation again when the input voltage crosses the rising UVLO-threshold level.

7.3.2 Enable and Shutdown

The device starts operation when the EN pin is set high and starts up with the soft-start as previously described. For proper operation, the EN pin must be terminated and must not be left floating.

Pulling the EN pin low forces the device into shutdown, with a shutdown quiescent current of 0.1 μA (typical). In this mode, the P and N-channel MOSFETs are turned off, the internal resistor feedback divider is disconnected, and the entire internal-control circuitry is switched off.

The EN input can be used to control power sequencing in a system with various DC-DC converters. The EN pin can be connected to the output of another converter, to drive the EN pin high and getting a sequencing of supply rails.

7.3.3 Thermal Shutdown

As soon as the junction temperature, TJ, exceeds 150°C (typical), the device goes into thermal shutdown. In this mode, the high-side and low-side MOSFETs are turned off. The device continues operation when the junction temperature falls below the thermal shutdown hysteresis.

7.4 Device Functional Modes

7.4.1 Soft Start

The device has an internal soft-start circuit that controls the ramp up of the output voltage and limits the inrush current during start-up. This limits input voltage drops when a battery or a high-impedance power source is connected to the input of the converter.

The soft-start system generates a monotonic ramp up of the output voltage and reaches the nominal output voltage which is typically 100 μs after EN pin was pulled high.

If the output voltage does not reach the target value by this time, such as in the case of heavy load, the converter then operates in a current limit mode set by the switch-current limits.

The device is able to start into a prebiased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage to the nominal value.

7.4.2 Power Save Mode

Connecting the MODE pin to GND enables the automatic PWM mode and power save mode operation. The converter operates in quasi-fixed frequency PWM mode at moderate to heavy loads and in the PFM (pulse frequency modulation) mode during light loads, which maintains high efficiency over a wide-load current range. In PFM mode, the device starts to skip switch pulses and generates only single pulses with an on time of tONmin. The PFM Mode frequency depends on the load current and the external inductor and output capacitor values. The PFM mode of the device is optimized for low output-voltage ripple if small external components are used. Even at low output currents, the PFM frequency is above the audible noise spectrum and makes this operation mode suitable for audio applications.

Use Equation 1 to estimate the on time tONmin.

Equation 1. TPS62231-Q1 TPS622314-Q1 eq1_ton_lvs941.gif

where

  • tON = High-side switch on time (ns)
  • VOUT= Output voltage (V)
  • VIN= Input voltage (V)

Therefore, use Equation 2 to calculate the approximate peak inductor current in PFM mode.

Equation 2. TPS62231-Q1 TPS622314-Q1 eq2_ilpf_lvs941.gif

where

  • ILPFMpeak = PFM inductor peak current (mA)
  • L = Inductance (µH)

Use Equation 3 to estimate the transition from PFM into PWM mode and from PWM into PFM.

Equation 3. TPS62231-Q1 TPS622314-Q1 eq6_ioutpfm_lvs941.gif

where

  • IOUT_PFM/PWM = Output current for transition from PFM to PWM mode and transition from PWM to PFM mode (mA)

7.4.3 Forced PWM Mode

Pulling the MODE pin high forces the converter to operate in a continuous-conduction PWM mode even at light load currents. The advantage is that the converter operates with a quasi-fixed frequency that allows simple filtering of the switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power save mode during light loads.

For additional flexibility, switch from power save mode to forced PWM mode during operation. This switching allows for efficient power management by adjusting the operation of the converter to the specific system requirements.

7.4.4 100% Duty-Cycle Low-Dropout Operation

The device starts to enter 100% duty-cycle mode when the input voltage comes close to the nominal output voltage. To maintain the output voltage, the high-side switch is turned on 100% for one or more cycles.

With further decreasing VIN, the high-side MOSFET switch is turned on completely. In this case the converter offers a low input-to-output voltage difference which is particularly useful in battery-powered applications to achieve the longest operation time by taking full advantage of the whole battery voltage range.

Use Equation 4 to calculate the minimum input voltage to maintain regulation which is dependent on the load current and output voltage.

Equation 4. TPS62231-Q1 TPS622314-Q1 eq3_vin_lvs941.gif

where

  • VOUTmax = nominal output voltage plus maximum output-voltage tolerance
  • IOUTmax = maximum output current plus inductor ripple current
  • RDS(on)max = maximum P-channel switch RDSon
  • RL = DC resistance of the inductor

7.4.5 Short-Circuit Protection

The device integrates a high-side and low-side MOSFET current limit to protect the device against heavy load or short circuit. The current in the switches is monitored by current-limit comparators. When the current in the P-channel MOSFET reaches the current limit, the P-channel MOSFET is turned off and the N-channel MOSFET is turned on to ramp down the current in the inductor. The high-side MOSFET switch can only turn on again when the current in the low-side MOSFET switch has decreased below the threshold of the current-limit comparator.