SLVSAI5B September   2010  – June 2016 TPS62290-Q1 , TPS62293-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Save Mode
        1. 8.3.1.1 Dynamic Voltage Positioning
        2. 8.3.1.2 100% Duty Cycle Low Dropout Operation
        3. 8.3.1.3 Undervoltage Lockout
      2. 8.3.2 Enable
      3. 8.3.3 Soft Start
      4. 8.3.4 Short-Circuit Protection
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPS62290DRV Adjustable 1.8 V
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Output Voltage Setting
          2. 9.2.1.2.2 Output Filter Design (Inductor and Output Capacitor)
            1. 9.2.1.2.2.1 Inductor Selection
            2. 9.2.1.2.2.2 Output Capacitor Selection
            3. 9.2.1.2.2.3 Input Capacitor Selection
        3. 9.2.1.3 Application Curves
      2. 9.2.2 TPS62290DRV Adjustable 3.3 V
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 TPS62293DRV Fixed 1.8 V
        1. 9.2.3.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resource
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS6229x devices are high-efficiency, synchronous, step-down DC-DC converters featuring Power Save Mode or 2.25-MHz fixed frequency operation.

9.2 Typical Applications

9.2.1 TPS62290DRV Adjustable 1.8 V

TPS62290-Q1 TPS62293-Q1 typ_opr18_lvsai5.gif Figure 7. TPS62290DRV Adjustable 1.8-V Schematic

9.2.1.1 Design Requirements

The design guideline provides a component selection to operate the device within the recommended operating condition.

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Output Voltage Setting

The output voltage can be calculated by Equation 2:

Equation 2. TPS62290-Q1 TPS62293-Q1 inl1_vout_lvs763.gif

with an internal reference voltage VREF typical 0.6 V.

To minimize the current through the feedback divider network, R2 must be 180 kΩ or 360 kΩ. The sum of R1 and R2 must not exceed approximately 1 MΩ, to keep the network robust against noise. An external feedforward capacitor C1 is required for optimum load transient response. The value of C1 must be in the range between 22 pF and 33 pF.

Route the FB line away from noise sources, such as the inductor or the SW line.

9.2.1.2.2 Output Filter Design (Inductor and Output Capacitor)

The TPS6229x-Q1 is designed to operate with inductors in the range of 1.5 µH to 4.7 µH and with output capacitors in the range of 4.7 µF to 22 µF. The part is optimized for operation with a 2.2-µH inductor and 10-µF output capacitor. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. For stable operation, the L and C values of the output filter must not fall below 1-µH effective inductance and 3.5-µF effective capacitance.

9.2.1.2.2.1 Inductor Selection

The inductor value has a direct effect on the ripple current. The selected inductor has to be rated for its DC resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VI or VO.

The inductor selection has also impact on the output voltage ripple in PFM mode. Higher inductor values lead to lower output voltage ripple and higher PFM frequency, lower inductor values lead to a higher output voltage ripple but lower PFM frequency.

Equation 3 calculates the maximum inductor current under static load conditions. The saturation current of the inductor must be rated higher than the maximum inductor current as calculated with Equation 4. This is recommended because during heavy load transient the inductor current rises above the calculated value.

Equation 3. TPS62290-Q1 TPS62293-Q1 q3_delta_lvs763_.gif
Equation 4. TPS62290-Q1 TPS62293-Q1 q4_ilmax_lvs763.gif

where

  • f = Switching Frequency (2.25 MHz typical)
  • L = Inductor Value
  • ΔIL = Peak to Peak inductor ripple current
  • ILmax = Maximum Inductor current

A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter.

Accepting larger values of ripple current allows the use of low inductance values, but results in higher output voltage ripple, greater core losses, and lower output current capability.

The total losses of the coil have a strong impact on the efficiency of the DC-DC conversion and consist of both the losses in the DC resistance (R(DC)) and the following frequency-dependent components.

  • The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
  • Additional losses in the conductor from the skin effect (current displacement at high frequencies)
  • Magnetic field losses of the neighboring windings (proximity effect)
  • Radiation losses

9.2.1.2.2.2 Output Capacitor Selection

The advanced fast-response voltage mode control scheme of the TPS6229x-Q1 allows the use of tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance overtemperature, become resistive at high frequencies.

At nominal load current, the device operates in PWM mode and the RMS ripple current is calculated as shown in Equation 5.

Equation 5. TPS62290-Q1 TPS62293-Q1 q5_irmsc_lvs763.gif

At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor as shown in Equation 6:

Equation 6. TPS62290-Q1 TPS62293-Q1 q6_deltav_lvs763.gif

At light load currents, the converter operates in Power Save Mode, and the output voltage ripple is dependent on the output capacitor and inductor value. Larger output capacitor and inductor values minimize the voltage ripple in PFM mode and tighten DC output accuracy in PFM mode.

9.2.1.2.2.3 Input Capacitor Selection

The buck converter has a natural pulsating input current; therefore, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For most applications, TI recommends a 10-µF ceramic capacitor. The input capacitor can be increased without any limit for better input voltage filtering.

Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on the input can induce ringing at the VIN pin. The ringing can couple to the output and be mistaken as loop instability or could even damage the part by exceeding the maximum ratings.

9.2.1.3 Application Curves

TPS62290-Q1 TPS62293-Q1 eff1_v18_io_lvs764.gif
Figure 8. Efficiency (Power Save Mode) vs Output Current
TPS62290-Q1 TPS62293-Q1 vo_acc_lvs764.gif
Figure 10. Output Voltage Accuracy (1.8-V Forced PWM Mode) vs Output Current
TPS62290-Q1 TPS62293-Q1 pfm_lt_lvs764.gif
Figure 12. PFM Load Transient
TPS62290-Q1 TPS62293-Q1 pfm_ltr_lvs764.gif
Figure 14. PWM Load Transient
TPS62290-Q1 TPS62293-Q1 typ_opr_pfm_lvs764.gif
Figure 16. Typical Operation vs PFM Mode
TPS62290-Q1 TPS62293-Q1 eff2_v18_io_lvs764.gif
Figure 9. Efficiency (Forced PWM Mode) vs Output Current
TPS62290-Q1 TPS62293-Q1 vo_acc4_lvs764.gif
Figure 11. Output Voltage Accuracy (1.8-V Power Save Mode) vs Output Current
TPS62290-Q1 TPS62293-Q1 pfm_lt2_lvs764.gif
Figure 13. PFM Line Transient
TPS62290-Q1 TPS62293-Q1 pfm_ltr2_lvs764.gif
Figure 15. PWM Line Transient
TPS62290-Q1 TPS62293-Q1 typ_opr_pwm_lvs764.gif
Figure 17. Typical Operation vs PWM Mode

9.2.2 TPS62290DRV Adjustable 3.3 V

TPS62290-Q1 TPS62293-Q1 typ_opr33_lvsai5.gif Figure 18. TPS62290DRV Adjustable 3.3-V Schematic

9.2.2.1 Design Requirements

For a 3.3-V output, the only change compared to the previous example is the feedback divider. A higher supply voltage is required to support the dropout to 3.3 V.

9.2.2.2 Detailed Design Procedure

For a 3.3-V output, the feedback-divider must be selected to provide the reference voltage of 0.6 V at FB-pin. Here, 820 kΩ for the upper resistor and 182 kΩ for the lower resistor was chosen.

9.2.2.3 Application Curves

TPS62290-Q1 TPS62293-Q1 eff3_v33_io_lvs764.gif
Figure 19. Efficiency (Power Save Mode) vs Output Current
TPS62290-Q1 TPS62293-Q1 vo_acc_lvs764.gif
Figure 21. Output Voltage Accuracy (1.8-V Forced PWM Mode) vs Output Current
TPS62290-Q1 TPS62293-Q1 eff4_v33_io_lvs764.gif
Figure 20. Efficiency (Forced PWM Mode) vs Output Current
TPS62290-Q1 TPS62293-Q1 vo_acc4_lvs764.gif
Figure 22. Output Voltage Accuracy (1.8-V Power Save Mode) vs Output Current

9.2.3 TPS62293DRV Fixed 1.8 V

TPS62290-Q1 TPS62293-Q1 typ_opr18_lvsai5.gif Figure 23. TPS62293DRV Fixed 1.8-V Schematic

9.2.3.1 Design Requirements

For a fixed 1.8-V output, the feedback dividers are not required. Obviously, a higher supply voltage is required to support the dropout to 1.8 V.