SLVSA67F February   2010  – April 2020 TPS62400-Q1 , TPS62402-Q1 , TPS62404-Q1 , TPS62405-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      TPS62402-Q1 Efficiency versus Output Current, VOUT1 and VOUT2
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Converter 1
      2. 9.1.2 Converter 2
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Enable
      2. 9.3.2 DEF_1 Pin Function
      3. 9.3.3 180° Out-of-Phase Operation
      4. 9.3.4 Short-Circuit Protection
      5. 9.3.5 Thermal Shutdown
      6. 9.3.6 EasyScale Interface: One-Pin Serial Interface for Dynamic Output-Voltage Adjustment
        1. 9.3.6.1 General
        2. 9.3.6.2 Protocol
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Save Mode
        1. 9.4.1.1 Dynamic Voltage Positioning
        2. 9.4.1.2 Soft Start
        3. 9.4.1.3 100% Duty-Cycle Low-Dropout Operation
        4. 9.4.1.4 Undervoltage Lockout
      2. 9.4.2 Mode Selection
    5. 9.5 Programming
      1. 9.5.1 Addressable Registers
        1. 9.5.1.1 Bit Decoding
        2. 9.5.1.2 Acknowledge
        3. 9.5.1.3 Mode Selection
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Output Voltage Setting
          1. 10.2.2.1.1 Converter 1 Adjustable Default Output-Voltage Setting: TPS62400-Q1
          2. 10.2.2.1.2 Converter 1 Fixed Default Output-Voltage Setting (TPS62402-Q1, TPS62404-Q1, and TPS62405-Q1)
          3. 10.2.2.1.3 Converter 2 Adjustable Default Output-Voltage Setting (TPS62400-Q1):
          4. 10.2.2.1.4 Converter 2 Fixed Default Output-Voltage Setting
        2. 10.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 10.2.2.2.1 Inductor Selection
          2. 10.2.2.2.2 Output-Capacitor Selection
          3. 10.2.2.2.3 Input Capacitor Selection
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

VIN = 3.6 V, VOUT1 = VOUT2 = 1.8 V, EN1 = EN2 = VIN, MODE = GND, L1 = L2 = 2.2 μH, COUT1 = COUT2 = 20 μF, TJ = –40°C to 125°C, typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN Input voltage range 2.5 6 V
IQ Operating quiescent current One converter, no load on the output. PFM mode enabled (MODE/DATA = GND) device not switching,
EN1 = 1 or EN2 = 1		 19 29 μA
Two converters, no load on the output. PFM mode enabled (MODE/DATA = GND) device not switching,
EN1 = EN2 = 1		 32 48
No load on the output, MODE/DATA = GND, for one converter, VOUTx = 1.575 V(1) 23
No load on the output, MODE/DATA = VIN, for one converter, VOUTx = 1.575 V(1) 3.6 mA
ISD Shutdown current EN1, EN2 = GND, VIN = 3.6 V(2) 1.2 3 μA
EN1, EN2 = GND, VIN ramped from 0 V to 3.6 V(3) 0.1 1
VUVLO Undervoltage lockout threshold Falling 1.5 2.35 V
Rising 2.4
ENABLE EN1, EN2
VIH High-level input voltage range, EN1, EN2 1.2 VIN V
VIL Low-level input voltage range, EN1, EN2 0 0.4 V
IIN Input bias current, EN1, EN2 EN1, EN2 = GND or VIN 0.05 1 μA
DEF_1 INPUT
VDEF_1H DEF_1 high-level digital input voltage range TPS62402-Q1, TPS62404-Q1, TPS62405-Q1 only 0.9 VIN V
VDEF_1L DEF_1 low-level digital input voltage range 0 0.4 V
IIN Input bias current DEF_1 DEF_1 = GND or VIN 0.01 1 μA
MODE/DATA
VIH High-level input voltage range, MODE/DATA 1.2 VIN V
VIL Low-level input voltage range, MODE/DATA 0 0.4 V
IIN Input bias current, MODE/DATA MODE/DATA = GND or VIN 0.01 1 μA
VOH Acknowledge output voltage high Open drain, through external pullup resistor VIN V
VOL Acknowledge output voltage low Open drain, sink current 500 μA 0 0.4 V
POWER SWITCH
rDS(on) P-channel MOSFET on-resistance, converter 1,2 VIN = VGS = 3.6 V 280 620 mΩ
ILK_PMOS P-channel leakage current VDS = 6 V 1 μA
rDS(on) N-channel MOSFET on-resistance converter 1,2 VIN = VGS = 3.6 V 200 450 mΩ
ILK_SW1/SW2 Leakage current into SW1 or SW2 pin Includes N-channel leakage current,
VIN = open, VSW = 6 V, EN = GND(4) 		6 7.5 μA
ILIMF Forward current limit PMOS and NMOS VOUT1 2.5 V ≤ VIN ≤ 6 V 0.68 0.8 0.92 A
VOUT2 0.85 1 1.15
TSD Thermal shutdown Increasing junction temperature 150 ºC
Thermal shutdown hysteresis Decreasing junction temperature 20 ºC
OUTPUT
VOUTx Adjustable output 1 or output 2 voltage range 0.6 VIN V
Vref Reference voltage 600 mV
VOUTx(PFM) DC output voltage accuracy adjustable and fixed output voltage(7) Voltage positioning active,
MODE/DATA = GND,
device operating in PFM mode,
VIN = 2.5 V to 5 V(5)(6) 		–1.5% 1% 2.5%
VOUTx(PWM) MODE/DATA = GND;
device operating in PWM mode,
VIN = 2.5 V to 6 V(6) 		–1% 0% 1%
VIN = 2.5 V to 6 V, MODE/DATA = VIN ,
Fixed PWM operation,
0 mA < IOUT1 < 400 mA ; 0 mA < IOUT2 < 600 mA(1) 		–1% 0% 1%
DC output voltage load regulation PWM operation mode 0.5 %/A
(1) Device is switching with no load on the output, L1 = L2 = 3.3 μH, value includes losses of the coil.
(2) These values are valid after enabling the device one time (EN1 or EN2 = high) and maintaining supply voltage VIN.
(3) These values are valid when the device is disabled (EN1 and EN2 low) and supply voltage VIN is powered up. The values remain valid until enabling the device the first time (EN1 or EN2 = high). After the first enable, Note 3 becomes valid.
(4) An internal resistor of 1 MΩ connects pins SW1 and SW2 to GND.
(5) Configuration L1 or L2 typ. 2.2 μH, COUTx typ 20 μF. See parameter measurement information, the output voltage ripple in PFM mode depends on the effective capacitance of the output capacitor; larger output capacitors lead to tighter output voltage tolerance.
(6) In power-save mode, the device typically enters PWM operation at IPSM = VIN / 32 Ω.
(7) Output voltage specification does not include tolerance of external voltage-programming resistors.