7.1.1 Operation

The TPS62410 includes two synchronous step-down converters. The converters operate with typically 2.25-MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. If power-save mode is enabled, the converters automatically enter power-save mode at light load currents and operate in pulse frequency modulation (PFM). During PWM operation the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch.

Each converter integrates two current limits, one in the P-channel MOSFET and another one in the N-channel MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is turned off and the N-channel MOSFET is turned on. If the current in the N-channel MOSFET is above the N-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit. The two DC/DC converters operate synchronized to each other. A 180° phase shift between converter 1 and converter 2 decreases the input RMS current.

7.3.1 Dynamic Voltage Positioning

This feature reduces the voltage undershoots and overshoots at load steps from light to heavy load and vice versa. It is activated in power-save mode operation. It provides more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off. This improves load transient behavior.

At light loads, in which the converter operate in PFM mode, the output voltage is regulated typically 1% higher than the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until it reaches the skip comparator low threshold set to –2% below the nominal value and enters PWM mode. During a load throw-off from heavy load to light load, the voltage overshoot is also minimized due to active regulation turning on the N-channel switch.

Figure 6. Dynamic Voltage Positioning

7.3.2 Undervoltage Lockout

The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery and disables the converters. The undervoltage lockout threshold is typically 1.5 V, maximum is 2.35 V. In case the default register values are overwritten by the Interface, the new values in the registers REG_DEF_1_Low and REG_DEF_2 remain valid as long the supply voltage does not fall under the undervoltage lockout threshold, independent of whether the converters are disabled.

7.3.3 Mode Selection

The MODE/DATA pin allows mode selection between forced PWM mode and power-save mode for both converters. Furthermore, this pin is a multi-purpose pin and provides (besides mode selection) a one-pin interface to receive serial data from a host to set the output voltage. This is described in the section EasyScale™ interface.

Connecting this pin to GND enables the automatic PWM and power-save mode operation. The converters operate in fixed-frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, maintaining high efficiency over a wide load current range.

Pulling the MODE/DATA pin high forces both converters to operate constantly in the PWM mode even at light load currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power-save mode during light loads. For additional flexibility it is possible to switch from power-save mode to forced PWM mode during operation. This allows efficient power management by adjusting the operation of the converter to the specific system requirements.

In case the operation mode will be changed from forced PWM mode (MODE/DATA = High) to power-save mode enable (MODE/DATA = 0) the power-save mode will be enabled after a delay time of typically t_timeout, which is a maximum of 520 μs.

The forced PWM mode operation is enabled immediately with pin MODE/DATA set to 1.

7.3.4 Enable

The device has for each converter a separate EN pin to start up each converter independently. If EN1 and EN2 are set to high, the corresponding converter starts up with soft-start.

Pulling EN1 and EN2 pin low forces the device into shutdown, with a shutdown quiescent current of typically 1.2 μA. In this mode, the P- and N-channel MOSFETs are turned off and the entire internal control circuitry is switched off. For proper operation, the EN1 and EN2 pins must be terminated and must not be left floating.

7.3.5 DEF_1 Pin Function

The DEF_1 pin is dedicated to converter 1 and works as an analog input for adjustable output voltage setting. Connecting an external resistor network to this pin adjusts the default output voltage to any value starting from 0.6 V to V_IN.

7.3.6 180° Out of Phase Operation

In PWM mode the converters operate with a 180° turnon phase shift of the PMOS (high-side) transistors. It prevents the high-side switches of both converters to be turned on simultaneously, and therefore smooths the input current. This feature reduces the surge current drawn from the supply.

7.3.7 Thermal Shutdown

As soon as the junction temperature, T_J, exceeds typically 150°C the device goes into thermal shutdown. In this mode, the P- and N-channel MOSFETs are turned off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis again.

7.4.1 Soft Start

The two converters have an internal soft-start circuit that limits the inrush current during start-up. During soft-start, the output voltage ramp up is controlled as shown in Figure 7.

Figure 7. Soft-Start

7.4.2 100% Duty Cycle Low Dropout Operation

The converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range; that is, the minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as:

Equation 1.

where

• Iout_max = maximum output current plus inductor ripple current
• RDSon_max = maximum P-channel switch RDSon
• R_L = DC resistance of the inductor
• Vout_max = nominal output voltage plus maximum output voltage tolerance

With decreasing load current, the device automatically switches into pulse-skipping operation in which the power stage operates intermittently based on load demand. By running cycles periodically the switching losses are minimized and the device runs with a minimum quiescent current maintaining high efficiency.

7.4.3 Power-Save Mode

The power-save mode is enabled with MODE/DATA pin set to 0 for both converters. If the load current of a converter decreases, this converter will enter power-save mode operation automatically. The transition to power-save mode of a converter is independent from the operating condition of the other converter. During power-save mode the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. The converter will position the output voltage in PFM mode to typically 1.01 × V_OUT. This voltage positioning feature minimizes voltage drops caused by a sudden load step.

In order to optimize the converter efficiency at light load the average inductor current is monitored. The device changes from PWM mode to power-save mode, if in PWM mode the inductor current falls below a certain threshold. The typical output current threshold depends on V_IN and can be calculated according to Equation 2 for each converter.

Equation 2: Average output current threshold to enter PFM mode

Equation 2.

Equation 3: Average output current threshold to leave PFM mode

Equation 3.

In order to keep the output voltage ripple in power-save mode low, the output voltage is monitored with a single threshold comparator (skip comparator). As the output voltage falls below the skip comparator threshold (skip comp) of 1.01 × V_OUTnominal, the corresponding converter starts switching for a minimum time period of typically 1 μs and provides current to the load and the output capacitor. Therefore the output voltage increases and the device maintains switching until the output voltage trips the skip comparator threshold (skip comp) again. At this moment all switching activity is stopped and the quiescent current is reduced to minimum. The load is supplied by the output capacitor until the output voltage has dropped below the threshold again. Hereupon the device starts switching again. The power-save mode is exited and PWM mode entered in case the output current exceeds the current IOUT_PFM_leave, or if the output voltage falls below a second comparator threshold, called skip comparator low (skip comp Low) threshold. This skip comparator low threshold is set to –2% below nominal V_out, and enables a fast transition from power-save mode to PWM mode during a load step. In power-save mode the quiescent current is reduced typically to 19 μA for one converter and 32 μA for both converters active. This single skip comparator threshold method in power-save mode results in a very low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor. Increasing output capacitor values minimizes the output ripple. The power-save mode can be disabled through the MODE/DATA pin set to high. Both converters then operate in fixed PWM mode. Power-save mode enable/disable applies to both converters.

7.4.4 Short Circuit Protection

Both outputs are short circuit protected with maximum output current = I_LIMF (P-MOS and N-MOS). Once the PMOS switch reaches its current limit, it will be turned off and the NMOS turned on. The PMOS only turns on again, once the current in the NMOS decreases below the NMOS current limit.

7.5.1 EasyScale™ Interface: One-Pin Serial Interface for Dynamic Output Voltage Adjustment

7.5.1.5 MODE Selection

Because of the MODE/DATA pin is used for two functions, interface and a mode selection, the device needs to determine when it has to decode the bit stream or to change the operation mode.

The device enters forced PWM mode operation immediately whenever the MODE/DATA pin turns to high level. The device stays also in forced PWM mode during the whole time of a protocol reception.

With a falling edge on the MODE/DATA pin the device starts bit decoding. If the MODE/DATA pin stays low for at least t_timeout, the device get’s an internal time-out and power-save mode operation is enabled.

A protocol which is sent within this time will be ignored, because the falling edge for the mode change will be first interpreted as start of the first bit. In this case, TI recommends to send first the protocol and change at the end of the protocol to power-save mode.

Figure 8. EasyScale™ Interface Protocol Overview

Table 1. EasyScale™ Interface Bit Description

BYTE	BIT NUMBER	NAME	TRANSMISSION DIRECTION	DESCRIPTION
Device Address Byte	7	DA7	IN	0 MSB device address
	6	DA6	IN	1
	5	DA5	IN	0
	4	DA4	IN	0
4Ehex	3	DA3	IN	1
	2	DA2	IN	1
	1	DA1	IN	1
	0	DA0	IN	0 LSB device address
Data Byte	7 (MSB)	RFA	IN	Request for acknowledge, if High, acknowledge condition will applied by the device
	6	A1		Address bit 1
	5	A0		Address bit 0
	4	D4		Data bit 4
	3	D3		Data bit 3
	2	D2		Data bit 2
	1	D1		Data bit 1
	0 (LSB)	D0		Data bit 0
		ACK	OUT	Acknowledge condition active 0, this condition will only be applied in case RFA bit is set. Open-drain output, Line needs to be pulled high by the host with a pullup resistor.
				This feature can only be used if the master has an open-drain output stage. In case of a push-pull output stage acknowledge condition may not be requested.

Figure 9. EasyScale™ Interface Protocol Without Acknowledge

Figure 10. EasyScale™ Interface Protocol Including Acknowledge

Figure 11. EasyScale™ Interface – Bit Coding

Figure 12. MODE/DATA Pin: Mode Selection

Figure 13. MODE/DATA Pin: Power-Save Mode and Interface Communication

Table 2. Addressable Registers for Adjustable Output Voltage Devices

Table 3. Selectable Output Voltages for Converter 1,
With DEF1 Pin as Analog Input

Table 4. Selectable Output Voltages for Converter 2,
(ADJ2 Connected to V_OUT)