SLVS676D JUNE   2006  – July 2015 TPS62420 , TPS62421

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Converter 1
      2. 8.1.2 Converter 2
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Dynamic Voltage Positioning
      2. 8.3.2 Undervoltage Lockout
      3. 8.3.3 Mode Selection
      4. 8.3.4 Enable
      5. 8.3.5 DEF_1 Pin Function
      6. 8.3.6 180° Out-of-Phase Operation
      7. 8.3.7 Thermal Shutdown
      8. 8.3.8 Short Circuit Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Soft-Start
      2. 8.4.2 100% Duty Cycle Low Dropout Operation
      3. 8.4.3 Power-Save Mode
    5. 8.5 Programming
      1. 8.5.1 EasyScale™ Interface: One-Pin Serial Interface for Dynamic Output Voltage Adjustment
        1. 8.5.1.1 General
        2. 8.5.1.2 Protocol
        3. 8.5.1.3 Bit Decoding
        4. 8.5.1.4 Acknowledge
        5. 8.5.1.5 MODE Selection
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Voltage Setting
        1. 9.1.1.1 Converter 1 Adjustable Default Output Voltage Setting
        2. 9.1.1.2 Converter 2
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application Circuit 1.5-V and 2.85-V Adjustable Outputs
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Output Filter Design (Inductor and Output Capacitor)
            1. 9.2.1.2.1.1 Inductor Selection
            2. 9.2.1.2.1.2 Output Capacitor Selection
            3. 9.2.1.2.1.3 Input Capacitor Selection
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Typical Application Circuit TPS62421
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Take care in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the main current paths as indicated in bold in Figure 36.

The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor.

Connect the GND pin of the device to the PowerPAD of the PCB and use this pad as a star point. For each converter use a common power GND node and a different node for the signal GND to minimize the effects of ground noise. Connect these ground nodes together to the PowerPAD (star point) underneath the IC. Keep the common path to the GND pin, which returns the small signal components and the high current of the output capacitors as short as possible to avoid ground noise. The output voltage sense lines (FB1, ADJ2, DEF_1) should be connected right to the output capacitor and routed away from noisy components and traces (that is, SW line). If the EasyScale™ interface is operated with high transmission rates, the MODE/DATA trace must be routed away from the ADJ2 line to avoid capacitive coupling into the ADJ2 pin. A GND guard ring between the MODE/DATA pin and ADJ2 pin avoids potential noise coupling.

11.2 Layout Example

TPS62420 TPS62421 layout_las676.gifFigure 36. Layout Diagram
TPS62420 TPS62421 pcb_lay_las676.gifFigure 37. PCB Layout