SLVSCH9E December 2014 – March 2022 TPS62406-Q1 , TPS62407-Q1 , TPS62422-Q1 , TPS62423-Q1 , TPS62424-Q1
PRODUCTION DATA
Three registers with a data content of 5 bits are addressable. With 5-bit data content, 32 different values for each register are available. Table 8-1 shows the addressable registers to set the output voltage when the DEF_1 pin works as a digital input. In this case, converter 1 has a related register for each DEF_1 pin condition, and one register for converter 2. A high or low condition on pin DEF_1 selects either the content of register REG_DEF_1_High or REG_DEF_1_Low, thus setting the output voltage of converter 1 according to the values in Selectable Output Voltage Converter 1, With Pin DEF_1 as Digital Input. Use of a precise internal resistor divider network to generate these output voltages makes external resistors unnecessary (less board space) and provides higher output-voltage accuracy. Enabling at least one of the converters (EN1 or EN2 is high) activates the interface. After the startup time tStart (170 μs), the interface is ready for data reception.
DEVICE | REGISTER | DESCRIPTION | DEF_1 PIN | A1 | A0 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|---|---|
TPS624xx-Q1 , | REG_DEF_1_High | Converter 1 output voltage setting for DEF_1 = High condition. The content of the register is active with the DEF_1 pin high. | High | 0 | 1 | Output voltage setting, see Table 8-3 | ||||
REG_DEF_1_Low | Converter 1 output voltage setting for DEF_1 = Low condition. | Low | 0 | 0 | Output voltage setting, see Table 8-3 | |||||
REG_DEF_2 | Converter 2 output voltage | Not applicable | 1 | 0 | Output voltage setting, see Table 8-4 | |||||
Do not use | 1 | 1 |