SLVSCH9E December   2014  – March 2022 TPS62406-Q1 , TPS62407-Q1 , TPS62422-Q1 , TPS62423-Q1 , TPS62424-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Converter 1
      2. 8.1.2 Converter 2
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable
      2. 8.3.2 DEF_1 Pin Function
      3. 8.3.3 180° Out-of-Phase Operation
      4. 8.3.4 Short-Circuit Protection
      5. 8.3.5 Thermal Shutdown
      6. 8.3.6 EasyScale Interface: One-Pin Serial Interface for Dynamic Output-Voltage Adjustment
        1. 8.3.6.1 General
        2. 8.3.6.2 Protocol
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Save Mode
        1. 8.4.1.1 Dynamic Voltage Positioning
        2. 8.4.1.2 Soft Start
        3. 8.4.1.3 100% Duty-Cycle Low-Dropout Operation
        4. 8.4.1.4 Undervoltage Lockout
      2. 8.4.2 Mode Selection
    5. 8.5 Programming
      1. 8.5.1 Addressable Registers
        1. 8.5.1.1 Bit Decoding
        2. 8.5.1.2 Acknowledge
        3. 8.5.1.3 Mode Selection
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Setting
          1. 9.2.2.1.1 Converter 1 Fixed Default Output-Voltage Setting
          2. 9.2.2.1.2 Converter 2 Fixed Default Output-Voltage Setting
        2. 9.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Output-Capacitor Selection
          3. 9.2.2.2.3 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Support Resources
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.1 Power-Save Mode

Setting the MODE/DATA pin to low for both converters enables power-save mode. If the load current of a converter decreases, this converter enters power-save-mode operation automatically. The transition of a converter to power-save mode is independent from the operating condition of the other converter. During power-save mode, the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. The converter positions the output voltage in PFM mode to typically 1% above nominal VOUTx. This voltage positioning feature minimizes voltage drops caused by a sudden load step.

In order to optimize the converter efficiency at light load, the device monitors average inductor current. The device changes from PWM mode to power-save mode if in PWM mode the inductor current falls below a certain threshold. The typical output current threshold, which one can calculate using Equation 1 for each converter, depends on VIN.

Equation 1: Average output current threshold to enter PFM mode

Equation 1. GUID-0EB0E1D0-2C55-4873-AEFB-1ADBA48F8399-low.gif

Equation 2: Average output current threshold to leave PFM mode

Equation 2. GUID-0A22BA16-FC72-4A9A-AD0A-EDB5204CA861-low.gif

To keep the output-voltage ripple in power-save mode low, a single threshold comparator (skip comparator) monitors the output voltage. As the output voltage falls below the skip-comparator threshold (skip comp) of 1% above nominal VOUTx, the corresponding converter starts switching for a minimum time period of typically 1 μs and provides current to the load and the output capacitor. Therefore, the output voltage increases and the device maintains switching until the output voltage trips the skip comparator threshold (skip comp) again. At this moment, all switching activity stops and the quiescent current reduces to minimum. The output capacitor supplies the load until the output voltage has dropped below the threshold again. Hereupon, the device starts switching again.

The converter leaves power-save mode and enters PWM mode if the output current exceeds the IOUT_PFM_leave current or if the output voltage falls below a second comparator threshold, called the skip-comparator-low (Skip Comp Low) threshold. This skip-comparator-low threshold is 2% below nominal VOUTx and enables a fast transition from power-save mode to PWM mode during a load step.

Power-save mode typically reduces the quiescent current to 19 μA for one converter and 32 μA for both converters active. This single-skip comparator threshold method in power-save mode results in a very low output-voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor. Increasing output capacitor values minimizes the output ripple. One can disable the power-save mode by setting the MODE/DATA pin to high. Both converters then operate in fixed PWM mode. Power-save mode enable or disable applies to both converters.