SLVSCH9E December 2014 – March 2022 TPS62406-Q1 , TPS62407-Q1 , TPS62422-Q1 , TPS62423-Q1 , TPS62424-Q1
PRODUCTION DATA
The bit detection is based on a PWM scheme, where the criterion is the relation between the low time and high time of the low or high bit (tL_xB and tH_xB). Bit detection can be simplified to:
High bit: tH_HB > tL_HB, but with tH_HB at least 2× tL_HB, see Figure 8-3.
Low bit: tL_LB > tH_LB, but with tL_LB at least 2× tH_LB, see Figure 8-3.
The bit detection starts with a falling edge on the MODE/DATA pin and ends with the next falling edge. Detection of a 0 or 1 depends on the relation between tL_xB and tH_xB.