SLUSDN9B November   2021  – July 2022 TPS62441-Q1 , TPS62442-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Schematic
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Precise Enable (EN)
      2. 9.3.2 COMP/FSET
      3. 9.3.3 MODE/SYNC
      4. 9.3.4 Spread Spectrum Clocking (SSC)
      5. 9.3.5 Undervoltage Lockout (UVLO)
      6. 9.3.6 Power-Good Output (PG)
      7. 9.3.7 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Pulse Width Modulation (PWM) Operation
      2. 9.4.2 Power Save Mode Operation (PWM and PFM)
      3. 9.4.3 100% Duty-Cycle Operation
      4. 9.4.4 Current Limit and Short Circuit Protection
      5. 9.4.5 Foldback Current Limit and Short Circuit Protection
      6. 9.4.6 Output Discharge
      7. 9.4.7 Soft Start
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Programming the Output Voltage
      2. 10.1.2 External Component Selection
        1. 10.1.2.1 Inductor Selection
        2. 10.1.2.2 Capacitor Selection
          1. 10.1.2.2.1 Input Capacitor
          2. 10.1.2.2.2 Output Capacitor
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Over operating junction temperature range (TJ = –40°C to +150°C) and VIN = 2.75 V to 6 V. Typical values at VIN = 5 V and TJ = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current EN1 or EN2 = VIN, no load, device is not switching, TJ = 25°C, MODE = GND, one converter enabled 27 µA
IQ Quiescent current EN1 or EN2 = VIN, no load, device is not switching, MODE = GND, one converter enabled 22 66 µA
IQ Quiescent current EN1 = EN2 = VIN, no load, device is not switching, TJ = 25°C, MODE = GND, both converters enabled 38 µA
IQ Quiescent current EN1 = EN2 = VIN, no load, device is not switching, MODE = GND, both converters enabled 33 80 µA
ISD Shutdown current EN1 = EN2 = low, at TJ = 25°C 2 µA
ISD Shutdown current EN1 = EN2 = GND, nominal value at TJ = 25°C, maximum value at TJ = 150°C 1.5 26 µA
VUVLO Undervoltage lockout threshold VIN rising 2.5 2.6 2.75 V
VIN falling 2.3 2.5 2.6 V
TJSD Thermal shutdown threshold TJ rising 170 °C
Thermal shutdown hysteresis TJ falling 15 °C
CONTROL AND INTERFACE
VEN,IH Input-threshold voltage at EN1, EN2, rising edge 1.06 1.1 1.15 V
VEN,IL Input-threshold voltage at EN1, EN2, falling edge 0.96 1.0 1.05 V
IEN,LKG Input leakage current into EN1, EN2 VIH = VIN or VIL = GND 450 nA
VIH High-level input-threshold voltage at MODE/SYNC 1.1 V
VIL Low-level input-threshold voltage at MODE/SYNC 0.3 V
ILKG Input leakage current into MODE/SYNC 700 nA
tDelay Enable delay time Time from ENx high to device starts switching, VIN applied already 110 200 300 µs
tDelay Enable delay time if one converter already enabled Time from ENx high to device starts switching, VIN applied already 100 µs
tRamp Output voltage ramp time Time from device starts switching to power good; the device is not in current limit 0.7 1.1 1.5 ms
fSYNC Frequency range on MODE/SYNC pin for synchronization 2 4 MHz
Resistance from COMP/FSET to GND for logic low Internal frequency setting with
f = 2.25 MHz		 0 2.5 kΩ
Voltage on COMP/FSET for logic high Internal frequency setting with
f = 2.25 MHz		 VIN V
VTH_PG UVP power-good threshold voltage;
DC level		 Rising (%VFB) 94% 96.5% 99%
VTH_PG UVP power-good threshold voltage;
DC level		 Falling (%VFB) 92% 94.5% 97%
VTH_PG OVP power-good threshold voltage;
DC level		 Rising (%VFB) 104% 107% 110%
OVP power-good threshold voltage;
DC level		 Falling (%VFB) 102% 104.5% 107%
VPG,OL Low-level output voltage at PG ISINK_PG = 2 mA 0.07 0.3 V
IPG,LKG Input leakage current into PG VPG = 5 V 100 nA
tPG PG deglitch time For a high-level to low-level transition on the power-good output 40 µs
OUTPUT
VFB1, VFB2 Feedback voltage 0.6 V
IFB1,LKG, IFB2,LKG Input leakage current into FB VFB = 0.6 V 1 80 nA
VFB1, VFB2 Feedback voltage accuracy PWM, VIN ≥ VOUT + 1 V –1% 1%
VFB1, VFB2 Feedback voltage accuracy PFM, VIN ≥ VOUT + 1 V, VOUT ≥ 1.5 V, Co,eff  ≥ 22 µF, L = 0.47 µH –1% 2.5%
VFB1, VFB2 Feedback voltage accuracy PFM, VIN ≥ VOUT + 1 V, 1 V ≤ VOUT < 1.5 V, Co,eff  ≥ 47 µF, L = 0.47 µH –1% 2.5%
Load regulation PWM 0.05 %/A
Line regulation PWM, IOUT = 1 A, VIN ≥ VOUT + 1 V 0.02 %/V
RDIS Output discharge resistance 50 150 Ω
fSW PWM switching frequency range See the FSET pin functionality about setting the switching frequency. 1.8 2.25 4 MHz
fSW PWM switching frequency With COMP/FSET tied to GND or VIN 2.025 2.25 2.475 MHz
fSW PWM switching frequency tolerance Using a resistor from COMP/FSET to GND –16% 17%
ton,min Minimum on time of high-side FET VIN ≥ 3.3 V 50 75 ns
ton,min Minimum on time of low-side FET 30 ns
RDS(ON) High-side FET on-resistance VIN ≥ 5 V 55 100 mΩ
Low-side FET on-resistance VIN ≥ 5 V 25 50 mΩ
High-side MOSFET leakage current VIN = 6 V; V(SW) = 0 V 1 86 µA
Low-side MOSFET leakage current V(SW) = 6 V 1 205 µA
ILIMH High-side FET switch current limit DC value, for the TPS62442;
VIN = 3 V to 6 V		 3.8 4.7 5.5 A
ILIMH High-side FET switch current limit DC value, for the TPS62441;
VIN = 3 V to 6 V		 2.1 2.6 3.1 A
ILIMNEG Low-side FET negative current limit DC value –1.8 A