SLVS651B May   2006  – December 2015 TPS62510

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Tracking (OVT)
      2. 7.3.2 Power Good
      3. 7.3.3 Undervoltage Lockout
      4. 7.3.4 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Soft Start
      2. 7.4.2 100% Duty Cycle Low Dropout Operation
      3. 7.4.3 Power Save Mode Operation (MODE)
      4. 7.4.4 Power Save Mode Transition Thresholds
      5. 7.4.5 Short-Circuit Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor Selection
        2. 8.2.2.2 Output Filter Design (Inductor and Output Capacitor)
        3. 8.2.2.3 Setting the Output Voltage Using the Feedback Resistor Divider
        4. 8.2.2.4 Inductor Selection
      3. 8.2.3 Application Curves
    3. 8.3 System Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VS Supply voltage at PVIN, AVIN –0.3 4 V
Voltage at EN, MODE, OVT, FB, PG(2) –0.3 4 V
Voltage at SW(2) –0.3 VIN + 0.3 V
TJ Operating junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage on pins PVIN and AVIN 1.8 3.8 V
VOUT Output voltage 0.6 VIN V
IOUT Output current, VIN = 1.8 V to 3.6 V 1500 mA
L Inductor value 2.2 μH
CIN Input capacitor value(1) 10 μF
COUT Output capacitance value(1) 22 μF
TA Operating ambient temperature -40 85 °C
TJ Operating junction temperature –40 125 °C
(1) See Application and Implementation for more information.

6.4 Thermal Information

THERMAL METRIC(1) TPS62510 UNIT
DRC [VSON]
10 PINS
RθJA Junction-to-ambient thermal resistance 48.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 71.2 °C/W
RθJB Junction-to-board thermal resistance 23.0 °C/W
ψJT Junction-to-top characterization parameter 2.1 °C/W
ψJB Junction-to-board characterization parameter 23.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 4.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

VIN = 3.3 V, OVT = EN = VIN, MODE = GND, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN Input voltage 1.8 3.8 V
I(q) Power save mode quiescent current
AVIN + PVIN		 FB = FB nominal + 5%, MODE = Low 22 30 μA
PWM Mode quiescent current into AVIN MODE = High 4.4 5 mA
I(SD) Shutdown current into PVIN + AVIN EN = Low, SW = GND 0.1 5 μA
UVLO Undervoltage lockout threshold at AVIN V(AVIN) falling (1) 1.55 1.58 V
Undervoltage lockout hysteresis 150 mV
T(SD) Thermal shutdown threshold Increasing junction temperature 160 °C
Thermal shutdown hysteresis 20 °C
CONTROL SIGNALS EN, MODE
VIH High level input voltage VIN = 1.8 V to 3.8 V 1.2 V
VIL Low level input voltage 0.4 V
IIB Input bias current 0.01 0.1 μA
f(sync) MODE synchronization range 1.15 2.25 MHz
Duration of high or low level for synchronization signal(2) 75 ns
OUTPUT VOLTAGE TRACKING (OVT)
IIB Input bias current 0.001 0.05 μA
VOS OVT offset voltage VOS = V(OVT) - V(FB), 0.1 V < V(OVT) < 0.5 V –15 15 mV
POWER GOOD (PG)
V(th) Power good threshold Feedback voltage rising –7% VOUT –5% VOUT –3% VOUT V
Power good hysteresis 2% VOUT 7% VOUT V
VOL Low level voltage I(PG) = 1 mA 0.3 V
Ilkg Power good leakage current V(PG) = 3.8 V 1 100 nA
OUTPUT
RDS(on) P-channel MOSFET on-resistance VIN = V(GS)  = 1.8 V 330 mΩ
VIN = V(GS)  = 3.3 V 120 170
Ilkg P-channel leakage current VIN  = 3.6 V 10 μA
RDS(on) N-channel MOSFET on-resistance VIN = V(GS)  = 1.8 V 200 mΩ
VIN = V(GS)  = 3.3 V 80 130
Ilkg N-channel leakage current V(DS) = 3.6 V 10 μA
IF Forward current limit (P- and N-channel) 1.8 V < VIN < 3.8 V 1.75 2 2.25 A
fs Oscillator frequency MODE = High 1.3 1.5 1.7 MHz
Vref Reference voltage 0.6 V
VFB Feedback voltage (3) PFM operation VIN = (VOUT + 0.3 V) to 3.8 V –2% 5%
VIN = (VOUT + 0.2 V) to 3.8 V; VOUT= 1.8 V, (4)
C2 = 15 μF, L1= 2.1 μH (effective values),
IOUT = 0 mA to 150 mA		 –2% 2.5%
VIN = (VOUT + 0.3 V) to 3.8 V; VOUT= 2.5V, (4)
C2 = 15 μF, L1= 2.1 μH (effective values),
IOUT = 0 mA to 150 mA		 –1.3% 2.3%
PWM operation VIN = VOUT + 0.3 V –1% 1%
IFB Feedback bias current V(FB) = 0.6 V, EN = High 0.001 0.05 μA
Line Regulation VIN = VOUT + 0.3 V (minimum 1.8 V) to 3.8 V;
IOUT = 800 mA		 0 %/V
Load Regulation IOUT = 10 mA to 1500 mA, PWM mode 0.1 %/A
tSS Soft start time VOUT ramping from 5% to 95% of nominal value 750 μs
Leakage resistance from SW pin to GND VIN > VOUT, 0 V ≤ V(SW)  ≤ VIN 700 1000 kΩ
Leakage resistance from FB pin to GND EN = Low 17 23
(1) The undervoltage lockout threshold is detected at the AVIN pin. Current through the RC filter causes a UVLO trip at higher VIN
(2) The minimum and maximum duty cycle applied to the MODE pin is calculated as:
D(min) = 75 ns × f(sync) and D(max) = 1 - 75 ns × f(sync).
(3) When using the output voltage tracking function, the feedback regulates to the voltage applied to OVT as long as the OVT < 0.6 V.
(4) Minimum and maximum values established by characterization and not production tested. Includes line and load regulation in PFM mode operation. For the measurements, a proper PCB layout and usage of recommended inductors and capacitors are essential.

6.6 Typical Characteristics

TPS62510 iq_v_vi_low_lvs651.gif Figure 1. No Load Quiescent Current vs Input Voltage, MODE = Low
TPS62510 freq_v_t_lvs651.gif Figure 3. Frequency vs Temperature
TPS62510 rds_v_vi_nmos_lvs651.gif Figure 5. NMOS RDS(on) vs Input Voltage
TPS62510 iq_v_vi_high_lvs651.gif Figure 2. No Load Quiescent Current vs Input Voltage, MODE = High
TPS62510 rds_v_vi_lvs651.gif Figure 4. PMOS RDS(on) vs Input Voltage
TPS62510 vos_v_ovt_lvs651.gif Figure 6. FB Offset vs Voltage ON VOUT