SLVSBO4C October   2012  – December 2014 TPS62736 , TPS62737

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3  Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Voltage Options
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Step-Down (Buck) Converter Operation
      2. 9.3.2 Programming OUT Regulation Voltage and VIN_OK
      3. 9.3.3 Nano-Power Management and Efficiency
    4. 9.4 Device Functional Modes
      1. 9.4.1 Enable Controls
      2. 9.4.2 Startup Behavior
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 TPS62737 3-Resistor Typical Application Circuit
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Inductor Selection
          2. 10.2.1.2.2 Output Capacitor Selection
          3. 10.2.1.2.3 Input Capacitor Selection
          4. 10.2.1.2.4 Resistor Selection
        3. 10.2.1.3 Application Curves
      2. 10.2.2 TPS62736 4-Resistor Typical Application Circuit
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Layout

12.1 Layout Guidelines

To minimize switching noise generation, the step-down converter (buck) power stage external components must be carefully placed. The most critical external component for a buck power stage is its input capacitor. The bulk input capacitor (CIN1) and high frequency decoupling capacitor (CIN2) must be placed as close as possible between the power stage input (IN pin 1) and ground (VSS pin 12). Next, the inductor (L1) must be placed as close as possible beween the switching node (SW pin 13) and the output voltage (OUT pin 11). Finally, the output capacitor (COUT) should be placed as close as possible between the output voltage (OUT pin 11) and GND (VSS pin 12). In the diagram below, the input and output capacitor grounds are connected to VSS pin 12 through vias to the bottom-layer ground plane of the PCB.

To minimize noise pickup by the high impedance voltage setting nodes (VIN_OK_SET pin 8 and VOUT_SET pin 9), the external resistors (R1, R2 and R3) should be placed so that the traces connecting the midpoints of the string are as short as possible. In the diagram below, the connection to VOUT_SET is by a bottom layer trace.

The remaining pins are either NC pins, that should be connected to the PowerPAD™ as shown below, or digital signals with minimal layout restrictions.

In order to maximize efficiency at light load, the use of voltage level setting resistors > 1 MΩ is recommended. However, during board assembly, contaminants such as solder flux and even some board cleaning agents can leave residue that may form parasitic resistors across the physical resistors and/or from one end of a resistor to ground, especially in humid, fast airflow environments. This can result in the voltage regulation and threshold levels changing significantly from those expected per the installed resistor values. Therefore, it is highly recommended that no ground planes be poured near the voltage setting resistors. In addition, the boards must be carefully cleaned, possibly rotated at least once during cleaning, and then rinsed with de-ionized water until the ionic contamination of that water is well above 50 MΩ. If this is not feasible, then it is recommended that the sum of the voltage setting resistors be reduced to at least 5 times below the measured ionic contamination.

12.2 Layout Example

Layout_SLVSBO4.gifFigure 72. Recommended Layout, TPS62736
Layout_737_SLVSBO4.gifFigure 73. Recommended Layout, TPS62737