SLVSEC6D June   2019  – March 2020 TPS62840

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
      2.      Efficiency versus Load Current (VOUT = 1.8 V)
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Smart Enable and Shutdown
      2. 8.3.2 Soft Start
      3. 8.3.3 Mode Selection: Power-Save Mode (PFM/PWM) or Forced PWM Operation (FPWM)
      4. 8.3.4 Output Voltage Selection (VSET)
      5. 8.3.5 Undervoltage Lockout UVLO
      6. 8.3.6 Switch Current Limit / Short Circuit Protection
      7. 8.3.7 Output Voltage Discharge
      8. 8.3.8 Thermal Shutdown
      9. 8.3.9 STOP Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Save Mode Operation
      2. 8.4.2 Forced PWM Mode Operation
      3. 8.4.3 100% Mode Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Example
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

DLC
SON-8
TPS62840 Pinout_8.gif
DGR
HVSSOP-8
TPS62840 Pinout_8_DGR.gif
YBG
WCSP-6
TPS62840 Pinout_6.gif

Pin Functions

PIN I/O DESCRIPTION
NAME DLC
(SON-8)		 DGR
(HVSSOP-8)		 YBG
(WCSP-6)
VIN 2 6 B1 PWR VIN power supply pin. Connect the input capacitor close to this pin for best noise and voltage spike suppression. A 4.7-µF ceramic capacitor is required.
SW 7 2 B2 PWR The switch pin is connected to the internal MOSFET switches. Connect the inductor to this terminal.
GND 1 8 A1 PWR GND supply pin. Connect this pin close to the GND terminal of the input and output capacitors.
VSET 5 4 C2 IN Connecting a resistor to GND sets the output voltage when the converter is enabled. For the TPS62849, connect this pin to GND.
VOS 8 1 A2 IN Output voltage sense pin for the internal feedback divider network and regulation loop. When the converter is disabled, this pin discharges VOUT by an internal MOSFET. Connect this pin directly to the output capacitor with a short trace.
EN 4 5 C1 IN Enable pin. A high level enables the device and a low level turns the device off. The pin features an internal pulldown resistor, which is disabled once the device has started up and the output voltage is regulated. The pulldown resistor is activated again, once a low level has been detected.
STOP 6 n/a n/a IN STOP Switching pin. When this pin is logic high, the converter stops switching in order to provide a quiet supply rail. The output is powered from the charge available in the output capacitor. When this pin is logic low, the device immediately resumes operation. The pin features an internal pulldown resistor, which is disabled once a high level is detected at the input. The pulldown resistor is activated again, once a low level has been detected.
MODE 3 3 n/a IN MODE pin. A low level enables Power-Save Mode operation with an automatic transition between PFM and PWM modes. A high level forces the converter to operated in PWM mode. This pin can be toggled during operation. It must be terminated.
NC n/a 7 n/a This pin is not connected internally. Do not connect this pin.
EP n/a 9 n/a PWR Exposed thermal pad(1). The PowerPAD must be connected to GND.
(1) For more information about the PowerPAD, see the PowerPAD™ Thermally Enhanced Package application report.