SLVSFU8C January   2022  – June 2024 TPS62843

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Enable and Shutdown (EN)
      2. 7.3.2 Soft Start
      3. 7.3.3 VSET Pin: Output Voltage Selection
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Switch Current Limit, Short-Circuit Protection
      6. 7.3.6 Thermal Shutdown
      7. 7.3.7 Output Voltage Discharge
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Save Mode Operation
      2. 7.4.2 100% Mode Operation
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRL|6
  • YKA|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

VSET Pin: Output Voltage Selection

The output voltage is set with a single external resistor connected between the VSET pin and GND. After the device has been enabled and the control logic as well as the internal reference have been powered up, a R2D (resistor-to-digital) conversion is started to detect the external resistor, RSET, within the regulator start-up delay time, tStartup_delay. An internal current source applies current through the external resistor and an internal ADC reads back the resulting voltage level. Depending on the level, an internal feedback divider network is selected to set the correct output voltage. After this R2D conversion is finished, the current source is turned off to avoid current flow through the external resistor. The circuit can detect resistive values, high-level, low-level, and a pin-open.

For a proper reading, ensure that there is no additional current path or capacitance greater than 30pF total to GND during R2D conversion. Otherwise, the additional current to GND is interpreted as a lower resistor value and a false output voltage is set. Table 7-1 lists the correct resistor values for RSET to set the appropriate output voltages. The R2D converter is designed to operate with resistor values out of the E96 table and requires 1% resistor value accuracy. The external resistor RSET is not a part of the regulator feedback loop and has therefore no impact on the output voltage accuracy. Ensure that there is no other leakage path than the RSET resistor at the VSET pin during an undervoltage lockout event. Otherwise, a false output voltage is set.

Table 7-1 Output Voltage Setting
VSET Output Voltage Setting [V] RSET [Ω]
TPS628436 TPS628437 TPS628438
1 0.400 0.80 1.8 10.0k
2 0.425 0.85 1.9 12.1k
3 0.450 0.90 2.0 15.4k
4 0.475 0.95 2.1 18.7k
5 0.500 1.00 2.2 23.7k
6 0.525 1.05 2.3 28.7k
7 0.550 1.10 2.4 36.5k
8 0.575 1.15 2.5 44.2k
9 0.600 1.20 2.6 56.2k
10 0.625 1.25 2.7 68.1k
11 0.650 1.30 2.8 86.6k
12 0.675 1.35 2.9 105.0k
13 0.700 1.40 3.0 133.0k
14 0.725 1.45 3.1 162.0k
15 0.750 1.50 3.2 205.0k
16 0.775 1.55 3.3 249.0k or larger
17 0.8 1.6 3.4 VIN
0

1.0

1.8 3.6 GND