SLUSDU8F September   2019  – October 2023 TPS62860 , TPS62861

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power Save Mode
      2. 8.3.2  Forced PWM Operation
      3. 8.3.3  Smart Enable and Shutdown (EN)
      4. 8.3.4  Soft Start
      5. 8.3.5  Output Voltage Selection (VSEL) for TPS62860x
      6. 8.3.6  Output Voltage Selection (VSEL and I2C)
      7. 8.3.7  Forced PWM Mode During Output Voltage Change
      8. 8.3.8  Undervoltage Lockout (UVLO)
      9. 8.3.9  Power Good (PG)
      10. 8.3.10 Switch Current Limit and Short Circuit Protection
      11. 8.3.11 Thermal Shutdown
      12. 8.3.12 Output Voltage Discharge
    4. 8.4 Programming
      1. 8.4.1 Serial Interface Description
      2. 8.4.2 Standard- and Fast-Mode Protocol
      3. 8.4.3 I2C Update Sequence
      4. 8.4.4 I2C Register Reset
    5. 8.5 Register Map
      1. 8.5.1 Slave Address Byte
      2. 8.5.2 Register Address Byte
      3. 8.5.3 VOUT Register 1
      4. 8.5.4 VOUT Register 2
      5. 8.5.5 CONTROL Register
      6. 8.5.6 STATUS Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application, TPS628610
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application, TPS628600, TPS62860x
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

TJ = –40°C to +125°C, VIN = 3.6 V. Typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ(VIN) VIN quiescent current EN = VIN, IOUT = 0μA, VOUT = 1.2 V
device not switching, TJ = -40°C to +85°C		 2.3 4 µA
EN = VIN, IOUT = 0μA, VOUT = 1.2 V, device switching 2.5 µA
ISD(VIN) VIN shutdown supply current EN = GND, shutdown current into VIN
VSEL/MODE = GND, TJ = -40°C to +85°C		 120 250 nA
UVLO
VUVLO(R) VIN UVLO rising threshold VIN rising 1.65 1.75 V
VUVLO(F) VIN UVLO falling threshold VIN falling 1.56 1.7 V
VUVLO(H) VIN UVLO hysteresis 100 mV
LOGIC PINs
VIH High-level input voltage threshold 0.8 V
VIL Low-level input voltage threshold 0.4 V
ILKG Input leakage current into SDA, SCL, VSEL Pin connected to VIN 10 25 nA
EN internal pull-down resistance EN pin to GND 0.5 MΩ
ILKG Input Leakage into EN Pin connected to VIN 10 25 nA
VOUT VOLTAGE
VOUT Output Voltage Accuracy PWM Mode, no load, TJ = 25°C to 85°C -1 +1 %
VOUT Output Voltage Accuracy PWM Mode, no load, TJ = -40°C to 125°C -2 +1.7 %
IVOS(LKG) VOS input leakage current EN = VIN, VOUT = 1.2 V (internal 12MΩ resistor divider),
TJ = -40°C to +85°C		 100 400 nA
SWITCHING FREQUENCY
fSW(FCCM) Switching frequency, TPS62861x VIN = 3.6V, VOUT =1.2V, PWM operation 4 MHz
fSW(FCCM) Switching frequency, TPS62860x VIN = 3.6V, VOUT =1.2V, PWM operation 1.5 MHz
STARTUP
Internal fixed soft-start time from VOUT = 0V to 95% of VOUT nominal 0.125 0.2 ms
EN HIGH to start of switching delay 500 1000 µs
POWER STAGE
RDSON(HS) High-side MOSFET on-resistance IOUT = 500 mA 120 170 mΩ
RDSON(LS) Low-side MOSFET on-resistance IOUT = 500 mA 80 115 mΩ
OVERCURRENT PROTECTION
IHS(OC) High-side peak current limit TPS628610 1.3 1.45 1.55 A
ILS(OC) Low-side valley current limit TPS628610 1.2 1.35 1.45 A
IHS(OC) High-side peak current limit TPS628601 0.95 1.1 1.2 A
ILS(OC) Low-side valley current limit TPS628601 0.85 1.0 1.1 A
ILS(NOC) Low-side negative current limit Sinking current limit on LS FET 0.8 A
POWER GOOD
VPGTH Power Good threshold PGOOD low, VOS falling 93%
VPGTH Power Good threshold PGOOD high, VOS rising 96%
tPG:DLY Power good deglitch delay PG rising edge 16 µs
IPG;LKG Input leakage current into PG-pin VPG = 5.0V 10 100 nA
PG-pin output low-level voltage IPG = 1mA 400 mV
OUTPUT DISCHARGE
Output discharge resistor on VOS pin EN = GND, IVOS = –10 mA into VOS pin
TJ = -40°C to +85°C		 7 11 Ω
THERMAL SHUTDOWN
TJ(SD) Thermal shutdown threshold (1) Temperature rising, PWM Mode 160 °C
TJ(HYS) Thermal shutdown hysteresis (1) 20 °C
(1) Specified by design. Not production tested.