SLUSDU8F September   2019  – October 2023 TPS62860 , TPS62861

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power Save Mode
      2. 8.3.2  Forced PWM Operation
      3. 8.3.3  Smart Enable and Shutdown (EN)
      4. 8.3.4  Soft Start
      5. 8.3.5  Output Voltage Selection (VSEL) for TPS62860x
      6. 8.3.6  Output Voltage Selection (VSEL and I2C)
      7. 8.3.7  Forced PWM Mode During Output Voltage Change
      8. 8.3.8  Undervoltage Lockout (UVLO)
      9. 8.3.9  Power Good (PG)
      10. 8.3.10 Switch Current Limit and Short Circuit Protection
      11. 8.3.11 Thermal Shutdown
      12. 8.3.12 Output Voltage Discharge
    4. 8.4 Programming
      1. 8.4.1 Serial Interface Description
      2. 8.4.2 Standard- and Fast-Mode Protocol
      3. 8.4.3 I2C Update Sequence
      4. 8.4.4 I2C Register Reset
    5. 8.5 Register Map
      1. 8.5.1 Slave Address Byte
      2. 8.5.2 Register Address Byte
      3. 8.5.3 VOUT Register 1
      4. 8.5.4 VOUT Register 2
      5. 8.5.5 CONTROL Register
      6. 8.5.6 STATUS Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application, TPS628610
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application, TPS628600, TPS62860x
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 I2C Interface Timing Characteristics

PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT
fSCL SCL Clock Frequency Standard mode 100 kHz
Fast mode 400 kHz
Fast mode plus 1 MHz
tBUF Bus Free Time Between a STOP and START Condition Standard mode 4.7 µs
Fast mode 1.3 µs
Fast mode plus 0.5 µs
tHD, tSTA Hold Time (Repeated) START condition Standard mode 4 µs
Fast mode 600 ns
Fast mode plus 260 ns
tLOW LOW Period of the SCL Clock Standard mode 4.7 µs
Fast mode 1.3 µs
Fast mode plus 0.5 µs
tHIGH HIGH Period of the SCL Clock Standard mode 4 µs
Fast mode 600 ns
Fast mode plus 260 ns
tSU, tSTA Setup Time for a Repeated START Condition Standard mode 4.7 µs
Fast mode 600 ns
Fast mode plus 260 ns
tSU, tDAT Data Setup Time Standard mode 250 ns
Fast mode 100 ns
Fast mode plus 50 ns
tHD, tDAT Data Hold Time Standard mode 0 3.45 µs
Fast mode 0 0.9 µs
Fast mode plus 0 µs
tRCL Rise Time of SCL Signal Standard mode 1000 ns
Fast mode 20+0.1CB 300 ns
Fast mode plus 120 ns
tRCL1 Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge BIT Standard mode 20+0.1CB 1000 ns
Fast mode 20+0.1CB 300 ns
Fast mode plus 120 ns
tFCL Fall Time of SCL Signal Standard mode 20+0.1CB 300 ns
Fast mode 300 ns
Fast mode plus 120 ns
tRDA Rise Time of SDA Signal Standard mode 1000 ns
Fast mode 20+0.1CB 300 ns
Fast mode plus 120 ns
tFDA Fall Time of SDA Signal Standard mode 300 ns
Fast mode 20+0.1CB 300 ns
Fast mode plus 120 ns
tSU, tSTO Setup Time of STOP Condition Standard mode 4 µs
Fast mode 600 ns
Fast mode plus 260 ns
CB Capacitive Load for SDA and SCL Standard mode 400 pF
Fast mode 400 pF
Fast mode plus 550 pF
(1) All values referred to VIL MAX and VIH MIN levels in ELECTRICAL CHARACTERISTICS table.