SLVSG94C November   2023  – June 2024 TPS62914 , TPS62916 , TPS62918

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Smart Config (S-CONF)
      2. 6.3.2  Device Enable (EN/SYNC)
      3. 6.3.3  Device Synchronization (EN/SYNC)
      4. 6.3.4  Spread Spectrum Modulation
      5. 6.3.5  Output Discharge
      6. 6.3.6  Undervoltage Lockout (UVLO)
      7. 6.3.7  Power-Good Output
      8. 6.3.8  Noise Reduction and Soft-Start Capacitor (NR/SS)
      9. 6.3.9  Current Limit and Short-Circuit Protection
      10. 6.3.10 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Fixed Frequency Pulse Width Modulation
      2. 6.4.2 Low Duty Cycle Operation
      3. 6.4.3 High Duty Cycle Operation (100% Duty Cycle)
      4. 6.4.4 Second Stage L-C Filter Compensation (Optional)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 External Component Selection
          1. 7.2.2.2.1 Switching Frequency Selection
          2. 7.2.2.2.2 Inductor Selection for the First L-C Filter
          3. 7.2.2.2.3 Output Capacitor Selection
          4. 7.2.2.2.4 Ferrite Bead Selection for Second L-C Filter
          5. 7.2.2.2.5 Input Capacitor Selection
          6. 7.2.2.2.6 Setting the Output Voltage
          7. 7.2.2.2.7 Bootstrap Capacitor Selection
          8. 7.2.2.2.8 NR/SS Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Layout Guidelines

A proper layout is critical for the operation of any switched mode power supply, especially at high switching frequencies. Therefore, the PCB layout of the TPS6291x demands careful attention to make sure of best performance. A poor layout can lead to issues like bad line and load regulation, instability, increased EMI radiation, and noise sensitivity. Refer to the Five Steps to a Great PCB Layout for a Step-Down Converter analog design journal for a detailed discussion of general best practices. Specific recommendations for the device are listed below.

  • Place the input capacitor or capacitors as close as possible to the VIN and PGND pins of the device. This placement is the most critical component placement. Route the input capacitors directly to the VIN and PGND pins avoiding vias.
  • Place the inductor close to the SW pin. Minimize the copper area at the switch node.
  • Place the output capacitor ground close to the PGND pin and route directly avoiding vias. Minimize the length of the connection from the inductor to the output capacitor.
  • Connect the VO pin directly to the first output capacitor, COUT.
  • Connect sensitive traces, such as the connections to the NR/SS, VO, and FB pins with short traces and be routed away from any noise source, such as the SW pin.
  • Connect the PSNS pin directly to the system GND plane with a via.
  • Place the second L-C filter, Lf and Cf, near the load to reduce any radiated coupling around the second L-C filter
  • Avoid placing the ferrite bead in the keep out region as shown in Figure 7-23
  • Place the FB resistors, R1 and R2, close to the FB pin and route the VOUT connection from R1 to the load as a remote sense trace. If a second L-C filter is used, this connection must be made after Lf.
  • See the recommended layout implemented on the EVM and shown in the EVM user's guide, TPS62916EVM Evaluation Module, as well as in Figure 7-23.