SLVSFS6C May   2021  – March 2023 TPS629210-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Thermal Information - DYC Package
    6. 7.6 Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Mode Selection and Device Configuration (MODE/S-CONF Pin)
      2. 8.3.2 Adjustable VO Operation (External Voltage Divider)
      3. 8.3.3 Selectable VO Operation (VSET and Internal Voltage Divider)
      4. 8.3.4 Smart Enable with Precise Threshold
      5. 8.3.5 Power Good (PG)
      6. 8.3.6 Output Discharge Function
      7. 8.3.7 Undervoltage Lockout (UVLO)
      8. 8.3.8 Current Limit and Short Circuit Protection
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode Operation (Auto PFM/PWM)
      3. 8.4.3 AEE (Automatic Efficiency Enhancement)
      4. 8.4.4 100% Duty-Cycle Operation
      5. 8.4.5 Starting into a Prebiased Load
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Programming the Output Voltage
        3. 9.2.2.3 External Component Selection
          1. 9.2.2.3.1 Output Filter and Loop Stability
          2. 9.2.2.3.2 Inductor Selection
          3. 9.2.2.3.3 Capacitor Selection
            1. 9.2.2.3.3.1 Output Capacitor
            2. 9.2.2.3.3.2 Input Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Powering Multiple Loads
      2. 9.3.2 Inverting Buck-Boost (IBB)
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Electrical Characteristics

VI = 3 V to 17 V, TJ = -40 °C to +150 °C , Typical values at VI = 12 V and TA = 25 °C, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Operating Quiescent Current, (Power Save Mode) Iout = 0 mA,  device not switching 4 µA
IQ;PWM Operating Quiescent Current (PWM Mode) VIN=12V, VOUT=1.2V; Iout = 0 mA, device switching 5 mA
ISD Shutdown current into VIN pin EN = 0 V 0.25 3 µA
VUVLO Under Voltage Lock-Out VIN rising 2.85 2.95 3.0 V
Under Voltage Lock-Out VIN falling 2.65 2.75 2.85 V
VUVLO Under Voltage Lock-Out Hysteresis 200 mV
CONTROL & INTERFACE
ILKG EN Input leakage current EN=VIN 3 300 nA
VIH;MODE High-Level Input Voltage at MODE/S-CONF Pin 1.0 V
VIL;MODE Low-level input voltage at MODE/S_CONF Pin 0.15 V
VIH High-level input voltage at EN-Pin 0.97 1.0 1.03 V
VIL Low-level input voltage at EN-Pin 0.87 0.9 0.93 V
VPG Power good threshold VFB rising, referenced to VFB nominal 93% 96% 99%
VFB falling, referenced to VFB nominal 89% 93% 96%
VPG_HYS Power good threshold hysteresis  hysteresis 3%
tPG,DLY Power good delay time 32 µs
tPG,DLY Power good pull down resistance 10 Ω
VPG,OL Low-level output voltage at PG pin ISINK = 1 mA 0.1 V
IPG,LKG Input leakage current into PG pin VPG = 5 V 0.01 1 µA
POWER SWITCHES
RDS;ON High-side FET on resistance 250 mΩ
Low-side FET on resistance 85
ILIM High-side FET current limit 1.5 1.8 2.1 A
Low-side FET current limit 1.3 1.6 1.9 A
ILIM;SINK Low-side FET sink current limit 0.8 1 1.2 A
TSD Thermal Shutdown Threshold TJ rising 170 °C
Thermal Shutdown Hysteresis TJ falling 20
fSW Switching frequency 2.5-MHz selection (FPWM Mode) 2.5 MHz
fSW Switching frequency 1.0-MHz selection (FPWM Mode) 1.0 MHz
TON(MIN) Minimum On-time 40 ns
ILKG;SW Leakage current into SW-Pin EN = 0V, VSW = VOS = 5.5V 0.1 5 µA
OUTPUT
VO Output Voltage Regulation VSET Configuration selected, 0°C ≤ TJ ≤ 85°C -1% +1%
VO Output Voltage Regulation VSET Configuration selected, -40°C ≤ TJ ≤ 150°C (DRL Package) -1.4% +1.1%
VO Output Voltage Regulation VSET Configuration selected, VOUT ≤ 3.8V, -40°C ≤ TJ ≤ 150°C
(DYC Package)		 -1.4% +1.1%
VO Output Voltage Regulation VSET Configuration selected, VOUT ≥ 5.0V, -40°C ≤ TJ ≤ 150°C
(DYC Package)		 -1.6% +1.1%
VFB Feedback Regulation Voltage Adjustable Configuration selected 0.6 V
VFB Feedback Voltage Regulation FB-Option selected, 0°C ≤ TJ ≤ 85°C -0.75% +0.75%
VFB Feedback Voltage Regulation FB-Option selected, -40°C ≤ TJ ≤ 150°C -1.2% +0.75%
IFB Input leakage current into FB pin Adjustable configuration, VFB = 0.6 V 1 100 nA
Tdelay Start-up delay time IO = 0 mA, time from EN rising edge until start switching, External FB Configuration selected 700 1500 µs
Start-up delay time IO = 0 mA, time from EN rising edge until start switching, VSET Configuration selected 1000 1800 µs
TSS Soft-Start time IO = 0 mA after Tdelay, from 1st switching pulse until target VO 600 700 µs
RDISCH Active Discharge Resistance Discharge = ON - Option Selected, EN = LOW, 7.5 20 Ω